Page 1 Preliminary User’s Manual 78K0/KD1+ 8-Bit Single-Chip Microcontrollers µ PD78F0122H µ PD78F0123H µ PD78F0124H µ PD78F0124HD Document No. U16962EJ1V0UD00 (1st edition) Date Published February 2004 N CP(K) 2004 Printed in Japan...
Page 2 [MEMO] Preliminary User’s Manual U16962EJ1V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KD1+ and design and develop application systems and programs for these devices. The target products are as follows. µ 78K0/KD1+: PD78F0122H, 78F0123H, 78F0124H, 78F0124HD Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
Page 7 Differences Between 78K0/KD1+ and 78K0/KD1 Series Name 78K0/KD1+ 78K0/KD1 Item Mask ROM version None Available Flash Power supply Single power supply Two power supplies memory Self-programming function Available None version Option byte Ring-OSC can be stopped/cannot be None stopped selectable 2.1 V ±0.1 V (fixed) 2.85 V ±0.15 V or 3.5 V ±0.2 V selectable Note...
Page 8 Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 9 CONTENTS CHAPTER 1 OUTLINE ..........................16 Features ............................16 Applications..........................17 Ordering Information ......................... 17 Pin Configuration (Top View)....................18 K1 Family Lineup ........................20 1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup .....................20 1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup ...................23 Block Diagram ..........................26 Outline of Functions ........................
Page 10 3.3.1 Relative addressing ........................59 3.3.2 Immediate addressing........................60 3.3.3 Table indirect addressing....................... 61 3.3.4 Register addressing ........................61 Operand Address Addressing ....................62 3.4.1 Implied addressing......................... 62 3.4.2 Register addressing ........................63 3.4.3 Direct addressing........................... 64 3.4.4 Short direct addressing ........................65 3.4.5 Special function register (SFR) addressing..................
Page 11 5.8.1 Switching from Ring-OSC clock to high-speed system clock............118 5.8.2 Switching from high-speed system clock to Ring-OSC clock............119 5.8.3 Switching from high-speed system clock to subsystem clock............120 5.8.4 Switching from subsystem clock to high-speed system clock............121 5.8.5 Register settings...........................122 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00................123 Functions of 16-Bit Timer/Event Counter 00.................
Page 12 CHAPTER 10 WATCHDOG TIMER ..................... 210 10.1 Functions of Watchdog Timer ....................210 10.2 Configuration of Watchdog Timer ..................212 10.3 Registers Controlling Watchdog Timer ................. 212 10.4 Operation of Watchdog Timer....................215 10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by option byte ..215 10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software”...
Page 13 14.4.3 Dedicated baud rate generator .....................297 CHAPTER 15 SERIAL INTERFACE CSI10 ..................304 15.1 Functions of Serial Interface CSI10..................304 15.2 Configuration of Serial Interface CSI10 ................. 304 15.3 Registers Controlling Serial Interface CSI10 ................ 306 15.4 Operation of Serial Interface CSI10..................309 15.4.1 Operation stop mode ........................309 15.4.2 3-wire serial I/O mode ........................310 CHAPTER 16 INTERRUPT FUNCTIONS ....................
Page 14 21.4 Cautions for Power-on-Clear Circuit ..................367 CHAPTER 22 LOW-VOLTAGE DETECTOR ..................369 22.1 Functions of Low-Voltage Detector..................369 22.2 Configuration of Low-Voltage Detector ................. 369 22.3 Registers Controlling Low-Voltage Detector ................ 370 22.4 Operation of Low-Voltage Detector..................372 22.5 Cautions for Low-Voltage Detector ..................376 CHAPTER 23 OPTION BYTE.......................
Page 15 CHAPTER 28 PACKAGE DRAWING ....................436 CHAPTER 29 CAUTIONS FOR WAIT ....................437 29.1 Cautions for Wait ........................437 29.2 Peripheral Hardware That Generates Wait ................438 29.3 Example of Wait Occurrence ....................439 APPENDIX A DEVELOPMENT TOOLS ....................440 A.1 Software Package ........................
Page 16 CHAPTER 1 OUTLINE 1.1 Features µ Minimum instruction execution time can be changed from high speed (0.125 s: @ 16 MHz operation with high- µ speed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits ×...
Page 17 CHAPTER 1 OUTLINE 1.2 Applications Automotive equipment • System control for body electricals (power windows, keyless entry reception, etc.) • Sub-microcontrollers for control Home audio, car audio AV equipment PC peripheral equipment (keyboards, etc.) Household electrical appliances • Outdoor air conditioner units •...
Page 18 CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 52-pin plastic LQFP (10 × 10) 52 51 50 49 48 47 46 45 44 43 42 41 40 P75/KR5 P76/KR6 FLMD0 P77/KR7 P00/TI000 P01/TI010/TO00 P10/SCK10/TxD0 RESET P11/SI10/RxD0 P12/SO10 P13/TxD6 P130 P14/RxD6 P120/INTP0 14 15 16 17 18 19 20 21 22 23 24 25 26...
Page 19 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI7: Analog input P130: Port 13 Analog reference voltage P140: Port 14 Analog ground PCL: Programmable clock output Power supply for port RESET: Reset Ground for port RxD0, RxD6: Receive data FLMD0, FLMD1: Flash programming mode SCK10: Serial clock input/output INTP0 to INTP6: External interrupt input...
Page 20 CHAPTER 1 OUTLINE 1.5 K1 Family Lineup 1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup • 30-pin SSOP (7.62 mm 0.65 mm pitch) 78K0/KB1 78K0/KB1+ µ µ µ PD78F0103 PD780103 PD78F0103H Mask ROM: 24 KB, Single-power-supply flash memory: 24 KB, Two-power-supply RAM: 768 B RAM: 768 B flash memory: 24 KB, RAM: 768 B...
Page 21 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1 is shown below. Part Number 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins − − − − 48 K/ −...
Page 22 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1+ is shown below. Part Number 78K0/KB1+ 78K0/KC1+ 78K0/KD1+ 78K0/KE1+ 78K0/KF1+ Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins Internal Flash memory 8 K 16 K/24 K 16 K 24 K/32 K 16 K 24 K/32 K 16 K 24 K/32 K 48 K/60 K 60 K memory (bytes)
Page 23 CHAPTER 1 OUTLINE 1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup 64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch) • 64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch) • 64-pin plastic LQFP (14 × 14 mm, 0.8 mm pitch) •...
Page 24 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1 is shown below. Part Number V850ES/KE1 V850ES/KF1 V850ES/KG1 V850ES/KJ1 Item Number of pins 64 pins 80 pins 100 pins 144 pins − − − − − − − Internal Mask ROM 96/128 memory −...
Page 25 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1+ is shown below. Part Number V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ V850ES/KJ1+ Item Number of pins 64 pins 80 pins 100 pins 144 pins − − − − Internal Mask ROM 96/128 128/256 128/256 memory −...
Page 26 CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 16-bit timer/ Port 0 P00 to P03 event counter 00 TI000/P00 Port 1 P10 to P17 TOH0/P15 8-bit timer H0 Port 2 P20 to P27 TOH1/P16 Port 3 P30 to P33 8-bit timer H1 Port 6 P60 to P63 8-bit timer/...
Page 27 CHAPTER 1 OUTLINE 1.7 Outline of Functions (1/2) µ µ µ µ Item PD78F0122H PD78F0123H PD78F0124H PD78F0124HD Internal Flash memory (self 16 KB 24 KB 32 KB Note 1 memory programming supported) (bytes) Note 1 High-speed RAM 512 bytes 1 KB Memory space 64 KB High-speed system clock...
Page 28 CHAPTER 1 OUTLINE (2/2) µ µ µ µ Item PD78F0122H PD78F0123H PD78F0124H PD78F0124HD Vectored interrupt Internal sources External Key interrupt Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7). Reset • Reset using RESET pin •...
Page 29 CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AV , EV , and V . The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P27...
Page 30 CHAPTER 2 PIN FUNCTIONS (1) Port pins Pin Name Function After Reset Alternate Function Port 0. Input TI000 4-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. − Use of an on-chip pull-up resistor can be specified by a −...
Page 31 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name Function After Reset Alternate Function INTP0 Input External interrupt request input for which the valid edge (rising Input P120 edge, falling edge, or both rising and falling edges) can be INTP1 to INTP3 P30 to P32 specified INTP4...
Page 32 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (port 0) P00 to P03 function as a 4-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P03 function as a 4-bit I/O port.
Page 33 CHAPTER 2 PIN FUNCTIONS (f) TI50 This is a pin for inputting an external count clock to 8-bit timer/event counter 50. (g) TO50, TOH0, and TOH1 These are timer output pins. (h) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.
Page 34 CHAPTER 2 PIN FUNCTIONS 2.2.5 P60 to P63 (port 6) P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). P60 to P63 are N-ch open-drain pins.
Page 35 CHAPTER 2 PIN FUNCTIONS 2.2.10 AV This is the A/D converter reference voltage input pin. Note When A/D converter is not used, connect this pin to EV or V Note Connect port 2 directly to EV when it is used as a digital port. 2.2.11 AV This is the A/D converter ground potential pin.
Page 36 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2.
Page 37 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 8-A Pullup P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Type 3-C Type 9-C Comparator P-ch N-ch P-ch – Data (threshold voltage) N-ch Input enable...
Page 38 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-W Type 16 IN/OUT Feedback cut-off Data N-ch Output disable P-ch Input enable Middle-voltage input buffer Preliminary User’s Manual U16962EJ1V0UD...
Page 39 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/KD1+ can each access a 64 KB memory space. Figures 3-1 to 3-4 show the memory maps. Caution Regardless of the internal memory capacity, the initial value of the internal memory size switching register (IMS) of all products in the 78K0/KD1+ is fixed (IMS = CFH).
Page 40 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-1. Memory Map ( PD78F0122H) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH 3FFFH Program area Data memory 1000H...
Page 41 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD78F0123H) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH 5FFFH Program area Data memory 1000H...
Page 42 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-3. Memory Map ( PD78F0124H) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH 7FFFH Program area Data memory 1000H...
Page 43 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-4. Memory Map ( PD78F0124HD) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits Note 1 FB00H FAFFH 7FFFH Program area...
Page 44 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KD1+ products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure...
Page 45 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 78K0/KD1+ products incorporate the following internal high-speed RAMs. Table 3-4. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM µ 512 × 8 bits (FD00H to FEFFH) PD78F0122H µ 1024 × 8 bits (FB00H to FEFFH) PD78F0123H µ...
Page 46 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KD1+, based on operability and other considerations.
Page 47 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-6. Correspondence Between Data Memory and Addressing ( PD78F0123H) Special function registers (SFRs) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 1024 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 48 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-7. Correspondence Between Data Memory and Addressing ( PD78F0124H) Special function registers (SFRs) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 1024 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 49 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-8. Correspondence Between Data Memory and Addressing ( PD78F0124HD) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 50 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/KD1+ products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 51 CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
Page 52 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
Page 53 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15 to PC8...
Page 54 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 55 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions.
Page 56 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port register 0 √ √ − FF01H Port register 1 √...
Page 57 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF3CH Pull-up resistor option register 12 PU12 √ √...
Page 58 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (3/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits − √ − Note 1 FFACH Reset control flag register RESF √...
Page 59 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 60 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 61 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 62 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed.
Page 63 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 64 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code OP code [Illustration]...
Page 65 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 66 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 67 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces.
Page 68 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 69 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 70 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
Page 71 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AV and EV . The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P27...
Page 72 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions Pin Name Function After Reset Alternate Function Port 0. Input TI000 4-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. − Use of an on-chip pull-up resistor can be specified by a −...
Page 73 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-3. Port Configuration Item Configuration Control registers Port mode register (PM0, PM1, PM3, PM6, PM7, PM12, PM14) Port register (P0 to P3, P6, P7, P12 to P14) Pull-up resistor option register (PU0, PU1, PU3, PU7, PU12, PU14) Port Total: 39 (CMOS I/O: 26, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4)
Page 74 CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Page 75 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 PU01 P-ch Alternate function PORT Output latch P01/TI010/TO00 (P01) PM01 Alternate function PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal Preliminary User’s Manual U16962EJ1V0UD...
Page 76 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 PU02 P-ch PORT Output latch (P02) PM02 Alternate function PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal Preliminary User’s Manual U16962EJ1V0UD...
Page 77 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified 1-bit units by pull-up resistor option register 1 (PU1).
Page 78 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10/RxD0, (P11, P14) P14/RxD6 PM11, PM14 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U16962EJ1V0UD...
Page 79 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P12 and P15 PU12, PU15 P-ch PORT Output latch P12/SO10, (P12, P15) P15/TOH0 PM12, PM15 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U16962EJ1V0UD...
Page 80 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P13 PU13 P-ch PORT Output latch (P13) P13/TxD6 PM13 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U16962EJ1V0UD...
Page 81 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TOH1/INTP5, (P16, P17) P17/TI50/TO50/FLMD1 PM16, PM17 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U16962EJ1V0UD...
Page 82 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-10 shows a block diagram of port 2. Figure 4-10. Block Diagram of P20 to P27 A/D converter P20/ANI0 to P27/ANI7 Read signal...
Page 83 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
Page 84 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/INTP4/TI51/TO51 (P33) PM33 Alternate function PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal Preliminary User’s Manual U16962EJ1V0UD...
Page 85 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 6 Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The P60 to P63 pins are N-ch open-drain pins. RESET input sets port 6 to input mode.
Page 86 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
Page 87 CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 88 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 13 Port 13 is a 1-bit output-only port. Figure 4-16 shows a block diagram of port 13. Figure 4-16. Block Diagram of P130 PORT Output latch P130 (P130) Read signal WD××: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
Page 89 CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 14 Port 14 is a 1-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode using port mode register 14 (PM14). When the P140 pin is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Page 90 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12, PM14) • Port registers (P0 to P3, P6, P7, P12 to P14) •...
Page 91 CHAPTER 4 PORT FUNCTIONS Table 4-4. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name Alternate Function PM×× P×× Function Name × TI000 Input × TI010 Input TO00 Output × SCK10 Input Output TxD0 Output ×...
Page 92 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0 to P3, P6, P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read.
Page 93 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P03, P10 to P17, P30 to P33, P70 to P77, P120, or P140 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, PU7, PU12, and PU14.
Page 94 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit.
Page 95 CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three system clock oscillators are available. • High-speed system clock oscillator The high-speed system clock oscillator oscillates a clock of f = 2.0 to 16.0 MHz.
Page 96 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus Oscillation Main OSC Processor clock Main clock stabilization time control mode register control register select register register (PCC) (MCM) (OSTS) (MOC) MSTOP MCM0 OSTS2 OSTS1 OSTS0 CSS PCC2 PCC1 PCC0 Oscillation stabilization STOP...
Page 97 CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The following seven registers are used to control the clock generator. • Processor clock control register (PCC) • Ring-OSC mode register (RCM) • Main clock mode register (MCM) • Main OSC control register (MOC) •...
Page 98 CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Processor Clock Control Register (PCC) Note 1 Address: FFFBH After reset: 00H Symbol <7> <6> <5> <4> PCC2 PCC1 PCC0 Note 2 Control of high-speed system clock oscillator operation Oscillation possible Oscillation stopped Note 3 Subsystem clock feedback resistor selection On-chip feedback resistor used...
Page 99 CHAPTER 5 CLOCK GENERATOR Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM) 2. f : Main system clock oscillation frequency (high-speed system clock oscillation frequency or Ring- OSC clock oscillation frequency) 3. f : Ring-OSC clock oscillation frequency 4.
Page 100 CHAPTER 5 CLOCK GENERATOR (3) Main clock mode register (MCM) This register sets the CPU clock (high-speed system clock/Ring-OSC clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears MCM to 00H. Figure 5-4. Format of Main Clock Mode Register (MCM) Note Address: FFA1H After reset: 00H...
Page 101 CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the high-speed system clock oscillator operation when the CPU is operating with the Ring-OSC clock.
Page 102 CHAPTER 5 CLOCK GENERATOR (5) Oscillation stabilization time counter status register (OSTC) This is the status register of the high-speed system clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
Page 103 CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) This register is used to select the high-speed system clock oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the high-speed system clock selected as CPU clock.
Page 104 CHAPTER 5 CLOCK GENERATOR (7) System wait control register (VSWC) This register is used to control wait states when a high-speed CPU and a low-speed peripheral I/O are connected. VSWC can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears VSWC to 00H.
Page 105 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 High-speed system clock oscillator The high-speed system clock oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 16 MHz) connected to the X1 and X2 pins. An external clock can be input to the high-speed system clock oscillator. In this case, input the clock signal to the X1 pin and input the inverse signal to the X2 pin.
Page 106 CHAPTER 5 CLOCK GENERATOR Cautions 1. When using the high-speed system clock oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-9 and 5-10 to avoid an adverse effect from wiring capacitance. •...
Page 107 CHAPTER 5 CLOCK GENERATOR Figure 5-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
Page 108 CHAPTER 5 CLOCK GENERATOR 5.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows. Note XT1: Connect directly to EV or V XT2: Leave open Note After reset is released, the on-chip feedback resistor must be set so that it is not used (bit 6 (FRC) of...
Page 109 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. • High-speed system clock f • Ring-OSC clock f • Subsystem clock f •...
Page 110 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Timing Diagram of CPU Default Start Using Ring-OSC High-speed system clock Ring-OSC clock Subsystem clock RESET Switched by software High-speed system clock Ring-OSC clock CPU clock Operation stopped: 17/f High-speed system clock oscillation stabilization time: Note to 2 Note Check using the oscillation stabilization time counter status register (OSTC).
Page 111 CHAPTER 5 CLOCK GENERATOR A status transition diagram of this product is shown in Figure 5-14, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 5-3 and 5-4, respectively.
Page 112 CHAPTER 5 CLOCK GENERATOR Figure 5-14. Status Transition Diagram (2/4) (2) When “Ring-OSC can be stopped by software” is selected by option byte (when subsystem clock is used) Status 6 CPU clock: f : Oscillation stopped : Oscillating/ oscillation stopped Interrupt MCC = 0 MCC = 1...
Page 113 CHAPTER 5 CLOCK GENERATOR Figure 5-14. Status Transition Diagram (3/4) (3) When “Ring-OSC cannot be stopped” is selected by option byte (when subsystem clock is not used) HALT HALT HALT instruction Interrupt Interrupt instruction Interrupt HALT instruction Status 3 Status 1 Status 2 Note 2 MCM0 = 0...
Page 114 CHAPTER 5 CLOCK GENERATOR Figure 5-14. Status Transition Diagram (4/4) (4) When “Ring-OSC cannot be stopped” is selected by option byte (when subsystem clock is used) Status 5 CPU clock: f : Oscillation stopped : Oscillating Interrupt MCC = 0 MCC = 1 HALT instruction Status 4...
Page 115 CHAPTER 5 CLOCK GENERATOR Table 5-3. Relationship Between Operation Clocks in Each Operation Status Status High-Speed System Ring-OSC Oscillator Subsystem CPU Clock Prescaler Clock Clock Oscillator Clock After Supplied to Peripherals Oscillator Release MSTOP = 0 MSTOP = 1 Note 1 Note 2 Operation MCC = 0...
Page 116 CHAPTER 5 CLOCK GENERATOR 5.6 Time Required to Switch Between Ring-OSC Clock and High-Speed System Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and high- speed system clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch clock after switching MCM0 (refer to Table 5-5).
Page 117 CHAPTER 5 CLOCK GENERATOR 5.7 Time Required for CPU Clock Switchover The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on the pre-switchover clock for several instructions (refer to Table 5-6).
Page 118 CHAPTER 5 CLOCK GENERATOR 5.8 Clock Switching Flowchart and Register Setting 5.8.1 Switching from Ring-OSC clock to high-speed system clock Figure 5-15. Switching from Ring-OSC Clock to High-Speed System Clock (Flowchart) After reset PCC = 00H RCM = 00H ; Ring-OSC oscillation MCM = 00H Register value ;...
Page 119 CHAPTER 5 CLOCK GENERATOR 5.8.2 Switching from high-speed system clock to Ring-OSC clock Figure 5-16. Switching from High-Speed System Clock to Ring-OSC Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; High-speed system clock oscillation in high-speed system PCC.4 (CSS) = 0 ;...
Page 120 CHAPTER 5 CLOCK GENERATOR 5.8.3 Switching from high-speed system clock to subsystem clock Figure 5-17. Switching from High-Speed System Clock to Subsystem Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; High-speed system clock oscillation in high-speed system PCC.4 (CSS) = 0 ;...
Page 121 CHAPTER 5 CLOCK GENERATOR 5.8.4 Switching from subsystem clock to high-speed system clock Figure 5-18. Switching from Subsystem Clock to High-Speed System Clock (Flowchart) PCC.4 (CSS) = 1 ; Subsystem clock operation MCM = 03H No: High-speed system clock oscillating MCC = 1? ;...
Page 122 CHAPTER 5 CLOCK GENERATOR 5.8.5 Register settings The table below shows the statuses of the setting flags and status flags when each mode is set. Table 5-7. Clock and Register Setting Mode Setting Flag Status Flag PCC Register Register Register Register Register Register...
Page 123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. • Interval timer • PPG output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval.
Page 124 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Timer counter 16 bits (TM00) Register 16-bit timer capture/compare register: 16 bits (CR000, CR010) Timer input TI000, TI010 Timer output...
Page 125 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00) Address: FF10H, FF11H After reset: 0000H Symbol...
Page 126 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES001 ES000 Falling edge...
Page 127 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00).
Page 128 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 The following six registers are used to control 16-bit timer/event counter 00. • 16-bit timer mode control register 00 (TMC00) • Capture/compare control register 00 (CRC00) • 16-bit timer output control register 00 (TOC00) •...
Page 129 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear TO00 inversion timing selection Interrupt request generation mode selection Operation stop...
Page 130 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010). CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC00 to 00H. Figure 6-6.
Page 131 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger control via software No one-shot pulse trigger One-shot pulse trigger OSPE00...
Page 132 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and TI000 and TI010 pin input valid edges. PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM00 to 00H.
Page 133 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00 (TM00).
Page 134 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an interval timer. Setting The basic operation setting procedure is as follows.
Page 135 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Control Register Settings for Interval Timer Operation (2/2) (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM001 PRM000 PRM00 Selects count clock. Setting invalid (setting “10” is prohibited.) Setting invalid (setting “10” is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer.
Page 136 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-13 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1>...
Page 137 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-13. Control Register Settings for PPG Output Operation (2/2) (c) 16-bit timer output control register 00 (TOC00) OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 TOC00 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting “11”...
Page 138 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Configuration Diagram of PPG Output 16-bit timer capture/compare register 000 (CR000) Clear 16-bit timer counter 00 circuit (TM00) Noise TI000/P00 eliminator TO00/TI010/P01 16-bit timer capture/compare register 010 (CR010) Figure 6-15. PPG Output Operation Timing Count clock M −...
Page 139 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
Page 140 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set.
Page 141 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Configuration Diagram for Pulse Width Measurement with Free-Running Counter 16-bit timer counter 00 OVF00 (TM00) 16-bit timer capture/compare TI000 register 010 (CR010) INTTM010 Internal bus Figure 6-19. Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock 0000H...
Page 142 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 143 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 D2 + 2 TM00 count value TI000 pin input CR010 capture value INTTM010...
Page 144 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI000 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 145 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM00 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI000 pin input CR010 capture value...
Page 146 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001...
Page 147 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (refer to Figure 6-26 for the set value). <2> Set the count clock by using the PRM00 register. <3>...
Page 148 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-26. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (2/2) (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM001 PRM000 PRM00 Selects external clock. Specifies rising edge for pulse width detection. Setting invalid (setting “10”...
Page 149 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (refer to Figure 6-29 for the set value). <3>...
Page 150 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Control Register Settings in Square-Wave Output Mode (2/2) (d) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM001 PRM000 PRM00 Selects count clock. Setting invalid (setting “10” is prohibited.) Setting invalid (setting “10” is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output.
Page 151 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1>...
Page 152 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Free-running mode (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 used as compare register CR010 used as compare register...
Page 153 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock N − 1 M − 1 TM00 count 0000H 0001H N + 1 0000H M + 1 M + 2 CR010 set value CR000 set value...
Page 154 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00...
Page 155 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) Count clock − − TM00 count value 0000H 0001H 0000H N + 1 N + 2 M + 1 M + 2 CR010 set value...
Page 156 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions for 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Page 157 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (6) Operation of OVF00 flag <1> The OVF00 flag is also set to 1 in the following case. When any of the following modes is selected: the mode in which clear & start occurs on a match between TM00 and CR000, the mode in which clear &...
Page 158 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (8) Timer operation <1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI000/TI010 pins are not acknowledged.
Page 159 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output Figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
Page 160 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus 8-bit timer compare Selector INTTM51 register 51 (CR51) TI51/TO51/P33/INTP4 Note 1 Match 8-bit timer TO51/TI51/ counter 51 (TM51) P33/INTP4 Clear Note 2 Output latch PM33 (P33)
Page 161 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n)
Page 162 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match.
Page 163 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
Page 164 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 Note TCL512 TCL511 TCL510 Count clock selection TI51 falling edge TI51 rising edge (10 MHz) /2 (5 MHz) (625 kHz)
Page 165 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3>...
Page 166 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Note Address: FF43H After reset: 00H Symbol <7> <3> <2> <0> TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516...
Page 167 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50/FLMD1 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0.
Page 168 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
Page 169 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR5n = FFH Count clock TM5n FEH FFH 00H CR5n TCE5n INTTM5n Interrupt acknowledged...
Page 170 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 171 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.
Page 172 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-13. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM5n count value Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
Page 173 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. • Clear the port output latch (P17 or P33) Note Note and port mode register (PM17 or PM33) to 0. • TCL5n: Select the count clock. •...
Page 174 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-14. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n <5>...
Page 175 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 7-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change. Count clock TM5n N N + 1 N + 2...
Page 176 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Page 177 CHAPTER 8 8-BIT TIMERS H0 AND H1 8.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. • Interval timer • PWM output mode • Square-wave output • Carrier generator mode (8-bit timer H1 only) 8.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware.
Page 178 Figure 8-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H 8-bit timer H compare register compare register 00 (CMP00) 10 (CMP10) Decoder TOH0/P15 Selector Output latch...
Page 179 Figure 8-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode 8-bit timer H carrier register 1 (TMHMD1) control register 1 (TMCYC1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 8-bit timer H 8-bit timer H RMC1 NRZB1 NRZ1 compare compare register 1 1...
Page 180 CHAPTER 8 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. RESET input clears CMP0n to 00H. Figure 8-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) After reset: 00H Symbol...
Page 181 CHAPTER 8 8-BIT TIMERS H0 AND H1 8.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register 1 (TMCYC1) Note •...
Page 182 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H <7> <1> <0> TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) Note 1 CKS02...
Page 183 CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H0 is not guaranteed.
Page 184 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH After reset: 00H <7> <1> <0> TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) Note CKS12...
Page 185 CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 3. In the PWM output mode and carrier generator mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11).
Page 186 CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 187 CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4 Operation of 8-Bit Timers H0 and H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
Page 188 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n...
Page 189 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn...
Page 190 CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
Page 191 CHAPTER 8 8-BIT TIMERS H0 AND H1 <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active.
Page 192 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H ≤...
Page 193 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n CMP1n...
Page 194 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn INTTMHn...
Page 195 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n...
Page 196 CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output.
Page 197 CHAPTER 8 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal.
Page 198 CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 8-14. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11...
Page 199 CHAPTER 8 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/f Duty = High-level width : Carrier clock output width = (M + 1) : (N + M + 2) Cautions 1.
Page 200 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer Hn count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H Hn count value CMPn0...
Page 201 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer Hn count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H Hn count value CMPn0...
Page 202 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1...
Page 203 CHAPTER 9 WATCH TIMER 9.1 Functions of Watch Timer The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 9-1 shows the watch timer block diagram. Figure 9-1.
Page 204 CHAPTER 9 WATCH TIMER (1) Watch timer When the high-speed system clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 9-1. Watch Timer Interrupt Time Interrupt Time When Operated at f = 32.768 kHz When Operated at f = 10 MHz µ...
Page 205 CHAPTER 9 WATCH TIMER 9.2 Configuration of Watch Timer The watch timer includes the following hardware. Table 9-3. Watch Timer Configuration Item Configuration 5 bits × 1 Counter 11 bits × 1 Prescaler Control register Watch timer operation mode register (WTM) 9.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM).
Page 206 CHAPTER 9 WATCH TIMER Figure 9-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH After reset: 00H Symbol <1> <0> WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 Watch timer count clock selection (78.125 kHz) (32.768 kHz) WTM6 WTM5 WTM4...
Page 207 CHAPTER 9 WATCH TIMER 9.4 Watch Timer Operations 9.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the high-speed system clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts.
Page 208 CHAPTER 9 WATCH TIMER 9.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM).
Page 209 CHAPTER 9 WATCH TIMER 9.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bit 3 (WTM3) of WTM.
Page 210 CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, refer to CHAPTER 19 RESET FUNCTION.
Page 211 CHAPTER 10 WATCHDOG TIMER Table 10-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Ring-OSC Cannot Be Stopped Ring-OSC Can Be Stopped by Software • Selectable by software (f Note 1 Watchdog timer clock Fixed to f source stopped) •...
Page 212 CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 10-1. Block Diagram of Watchdog Timer Clock Output 16-bit...
Page 213 CHAPTER 10 WATCHDOG TIMER Figure 10-2. Format of Watchdog Timer Mode Register (WDTM) Address: FF98H After reset: 67H Symbol WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 WDTM Note 1 Note 1 WDCS4 WDCS3 Operation clock selection Ring-OSC clock (f High-speed system clock (f ×...
Page 214 CHAPTER 10 WATCHDOG TIMER (2) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. RESET input sets WDTE to 9AH. Figure 10-3.
Page 215 CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to the Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 216 CHAPTER 10 WATCHDOG TIMER 10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the high-speed system clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 217 CHAPTER 10 WATCHDOG TIMER 10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the high-speed system clock or Ring-OSC clock is being used. (1) When the CPU clock and the watchdog timer operation clock are the high-speed system clock (f ) when the STOP instruction is executed...
Page 218 CHAPTER 10 WATCHDOG TIMER (3) When the CPU clock is the Ring-OSC clock (f ) and the watchdog timer operation clock is the high-speed system clock (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is stopped until the timing of <1>...
Page 219 CHAPTER 10 WATCHDOG TIMER (4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped.
Page 220 CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.1 Functions of Clock Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. Figure 11-1 shows the block diagram of clock output controller.
Page 221 CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.3 Registers Controlling Clock Output Controller The following two registers are used to control the clock output controller. • Clock output selection register (CKS) • Port mode register 14 (PM14) (1) Clock output selection register (CKS) This register sets output enable/disable for clock output (PCL) and sets the output clock.
Page 222 CHAPTER 11 CLOCK OUTPUT CONTROLLER (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output, set PM140 and the output latch of P140 to 0. PM14 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM14 to FFH.
Page 223 CHAPTER 12 A/D CONVERTER 12.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI7.
Page 224 CHAPTER 12 A/D CONVERTER 12.2 Configuration of A/D Converter The A/D converter includes the following hardware. Table 12-1. Registers of A/D Converter Used on Software Item Configuration Registers A/D conversion result register (ADCR) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) (1) ANI0 to ANI7 pins...
Page 225 CHAPTER 12 A/D CONVERTER (6) A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register (SAR) to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its higher 10 bits (the lower 6 bits are fixed to 0).
Page 226 CHAPTER 12 A/D CONVERTER 12.3 Registers Used in A/D Converter The following five registers are used to control the A/D converter. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • A/D conversion result register (ADCR) •...
Page 227 CHAPTER 12 A/D CONVERTER Table 12-2. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Note Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates) Note Data of first conversion cannot be used.
Page 228 CHAPTER 12 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS to 00H. Figure 12-5.
Page 229 CHAPTER 12 A/D CONVERTER (3) A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from the most significant bit (MSB).
Page 230 CHAPTER 12 A/D CONVERTER (4) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the ADCR register) and the value of the power-fail comparison threshold register (PFT). PFM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PFM to 00H.
Page 231 CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Operations 12.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). µ <2> Set ADCE to 1 and wait for 14 s or longer. <3>...
Page 232 CHAPTER 12 A/D CONVERTER Figure 12-9. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 233 CHAPTER 12 A/D CONVERTER 12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression. ×...
Page 234 CHAPTER 12 A/D CONVERTER 12.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting bit 7 (PFEN) of the power-fail comparison mode register (PFM).
Page 235 CHAPTER 12 A/D CONVERTER (2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started.
Page 236 CHAPTER 12 A/D CONVERTER The setting methods are described below. • When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
Page 237 CHAPTER 12 A/D CONVERTER 12.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 238 CHAPTER 12 A/D CONVERTER (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0..000 to 0..001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
Page 239 CHAPTER 12 A/D CONVERTER (8) Conversion time This expresses the time since sampling has been started until digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time...
Page 240 CHAPTER 12 A/D CONVERTER (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AV pin and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 12-19, to reduce noise.
Page 241 CHAPTER 12 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 242 CHAPTER 12 A/D CONVERTER (11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 12-21 and Table 12-3.
Page 243 CHAPTER 12 A/D CONVERTER (13) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 12-22. Internal Equivalent Circuit of ANIn Pin ANIn Table 12-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 2.7 V 12 kΩ...
Page 244 CHAPTER 13 SERIAL INTERFACE UART0 13.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 245 CHAPTER 13 SERIAL INTERFACE UART0 13.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 13-1. Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0)
Page 246 Figure 13-1. Block Diagram of Serial Interface UART0 Filter SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial Asynchronous serial INTSR0 Reception control Receive buffer register 0 Baud rate interface operation mode interface reception error (RXB0) generator register 0 (ASIM0) status register 0 (ASIS0) Reception unit Internal bus 8-bit timer/...
Page 247 CHAPTER 13 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0).
Page 248 CHAPTER 13 SERIAL INTERFACE UART0 13.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. • Asynchronous serial interface operation mode register 0 (ASIM0) • Asynchronous serial interface reception error status register 0 (ASIS0) •...
Page 249 CHAPTER 13 SERIAL INTERFACE UART0 Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 250 CHAPTER 13 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears ASIS0 to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0.
Page 251 CHAPTER 13 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets BRGC0 to 1FH.
Page 252 CHAPTER 13 SERIAL INTERFACE UART0 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring-OSC clock, the operation of serial interface UART0 is not guaranteed.
Page 253 CHAPTER 13 SERIAL INTERFACE UART0 13.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 13.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode.
Page 254 CHAPTER 13 SERIAL INTERFACE UART0 13.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 255 CHAPTER 13 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 13-6 and 13-7 show the format and waveform example of the normal transmit/receive data. Figure 13-6. Format of Normal UART Transmit/Receive Data 1 data frame Start Parity...
Page 256 CHAPTER 13 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 257 CHAPTER 13 SERIAL INTERFACE UART0 (c) Transmission The T D0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0).
Page 258 CHAPTER 13 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the R D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the R D0 pin input is detected.
Page 259 CHAPTER 13 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated.
Page 260 CHAPTER 13 SERIAL INTERFACE UART0 13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 261 CHAPTER 13 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter.
Page 262 CHAPTER 13 SERIAL INTERFACE UART0 (3) Example of setting baud rate Table 13-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS00 Value TPS00...
Page 263 CHAPTER 13 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 264 CHAPTER 13 SERIAL INTERFACE UART0 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 265 CHAPTER 14 SERIAL INTERFACE UART6 14.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 266 CHAPTER 14 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
Page 267 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-2. LIN Reception Operation Wakeup Synchronous Synchronous Indent Data field Data field Checksum signal frame break field field field field Sleep Data Data Data Note 5 reception reception reception reception reception Note 2 13 bits reception Disable Enable...
Page 268 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0 INTP0 input Port mode Port input (PM120) switch control (ISC0) Output latch <ISC0> (P120) 0: Select INTP0 (P120) 1: Select RxD6 (P14) Selector...
Page 269 CHAPTER 14 SERIAL INTERFACE UART6 14.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 14-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Page 270 Figure 14-4. Block Diagram of Serial Interface UART6 Note TI000, INTP0 Filter INTSR6 Reception control INTSRE6 Receive shift register 6 (RXS6) Asynchronous serial Asynchronous serial Asynchronous serial interface Baud rate Receive buffer register 6 interface operation mode interface reception error control register 6 (ASICL6) generator (RXB6)
Page 271 CHAPTER 14 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6).
Page 272 CHAPTER 14 SERIAL INTERFACE UART6 14.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
Page 273 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity.
Page 274 CHAPTER 14 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears ASIS6 to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.
Page 275 CHAPTER 14 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 276 CHAPTER 14 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears CKSR6 to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 277 CHAPTER 14 SERIAL INTERFACE UART6 Remarks 1. Figures in parentheses apply to operation with f = 10 MHz. 2. f : High-speed system clock oscillation frequency 3. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6.
Page 278 CHAPTER 14 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASICL6 to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 279 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
Page 280 CHAPTER 14 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input source is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 281 CHAPTER 14 SERIAL INTERFACE UART6 14.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 282 CHAPTER 14 SERIAL INTERFACE UART6 14.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 283 CHAPTER 14 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 PM14 UART6 Pin Function Operation TxD6/P13 RxD6/P14 Note Note Note Note × ×...
Page 284 CHAPTER 14 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-13 and 14-14 show the format and waveform example of the normal transmit/receive data. Figure 14-13. Format of Normal UART Transmit/Receive Data 1.
Page 285 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...
Page 286 CHAPTER 14 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 287 CHAPTER 14 SERIAL INTERFACE UART6 (c) Normal transmission The T D6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
Page 288 CHAPTER 14 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
Page 289 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-16 shows an example of the continuous transmission processing flow. Figure 14-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6. Transmission completion interrupt occurs?
Page 290 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-17 shows the timing of starting continuous transmission, and Figure 14-18 shows the timing of ending continuous transmission. Figure 14-17. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6...
Page 291 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-18. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6...
Page 292 CHAPTER 14 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
Page 293 CHAPTER 14 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Page 294 CHAPTER 14 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 295 CHAPTER 14 SERIAL INTERFACE UART6 If the number of bits set by BRGC6 runs short, adjust the number of bits by setting the base clock of UART6. Figure 14-22. Example of Setting Procedure of SBF Transmission (Flowchart) Start Read BRGC6 register and save current set value of BRGC6 register to general- purpose register.
Page 296 CHAPTER 14 SERIAL INTERFACE UART6 SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, refer to Figure 14-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
Page 297 CHAPTER 14 SERIAL INTERFACE UART6 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 298 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-25. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6...
Page 299 CHAPTER 14 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
Page 300 CHAPTER 14 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 14-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS60...
Page 301 CHAPTER 14 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 302 CHAPTER 14 SERIAL INTERFACE UART6 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 303 CHAPTER 14 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 304 CHAPTER 15 SERIAL INTERFACE CSI10 15.1 Functions of Serial Interface CSI10 Serial interface CSI10 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption.
Page 305 CHAPTER 15 SERIAL INTERFACE CSI10 Figure 15-1. Block Diagram of Serial Interface CSI10 Internal bus Serial I/O shift Transmit buffer Output SI10/P11/R register 10 (SIO10) register 10 (SOTB10) selector SO10/P12 Output latch PM12 (P12) Output latch Transmit data controller Transmit controller Clock start/stop controller &...
Page 306 CHAPTER 15 SERIAL INTERFACE CSI10 15.3 Registers Controlling Serial Interface CSI10 Serial interface CSI10 is controlled by the following four registers. • Serial operation mode register 10 (CSIM10) • Serial clock selection register 10 (CSIC10) • Port mode register 1 (PM1) •...
Page 307 CHAPTER 15 SERIAL INTERFACE CSI10 (2) Serial clock selection register 10 (CSIC10) CSIC10 specifies the timing of the data transmission/reception and sets the serial clock. CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIC10 to 00H. Figure 15-3.
Page 308 CHAPTER 15 SERIAL INTERFACE CSI10 Cautions 1. When the Ring-OSC clock is selected as the clock supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI10 is not guaranteed. 2.
Page 309 CHAPTER 15 SERIAL INTERFACE CSI10 15.4 Operation of Serial Interface CSI10 Serial interface CSI10 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 15.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/T D0, P11/SI10/R D0, and P12/SO10 pins can be used as ordinary I/O port pins in this...
Page 310 CHAPTER 15 SERIAL INTERFACE CSI10 15.4.2 3-wire serial I/O mode The 3-wire serial I/O mode can be used for connecting peripheral ICs and display controllers that have a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10) lines.
Page 311 CHAPTER 15 SERIAL INTERFACE CSI10 The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins CSIE10 TRMD10 PM11 PM12 PM10 CSI10 Pin Function Operation SI10/RxD0/ SO10/P12 SCK10/ TxD0/P10 Note 1 Note 1 Note 1 Note 1 Note 1...
Page 312 CHAPTER 15 SERIAL INTERFACE CSI10 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10).
Page 313 CHAPTER 15 SERIAL INTERFACE CSI10 Figure 15-5. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1) SCK10 Read/write trigger SOTB10 55H (communication data) SIO10 CSOT10 INTCSI10 CSIIF10 SI10 (input AAH)
Page 314 CHAPTER 15 SERIAL INTERFACE CSI10 Figure 15-6. Timing of Clock/Data Phase (a) Type 1; CKP10 = 0, DAP10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 (b) Type 2; CKP10 = 0, DAP10 = 1 SCK10 SI10 capture SO10...
Page 315 CHAPTER 15 SERIAL INTERFACE CSI10 (3) Timing of output to SO10 pin (first bit) When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin. The output operation of the first bit at this time is described below. Figure 15-7.
Page 316 CHAPTER 15 SERIAL INTERFACE CSI10 (4) Output value of SO10 pin (last bit) After communication has been completed, the SO10 pin holds the output value of the last bit. Figure 15-8. Output Value of SO10 Pin (Last Bit) (1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0) SCK10 ( ←...
Page 317 CHAPTER 15 SERIAL INTERFACE CSI10 (5) SO10 output The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is cleared to 0. Table 15-3. SO10 Output Status Note 1 TRMD10 DAP10 DIR10 SO10 Output...
Page 318 CHAPTER 16 INTERRUPT FUNCTIONS 16.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated.
Page 319 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (1/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Note 3 Maskable INTLVI Low-voltage detection Internal 0004H INTP0 Pin input edge detection External 0006H INTP1...
Page 320 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (2/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type − − Software BRK instruction execution 003EH − − − Reset RESET Reset input...
Page 321 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP6) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...
Page 322 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus Interrupt Vector table Priority controller request address generator interrupt detector 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus Interrupt...
Page 323 CHAPTER 16 INTERRUPT FUNCTIONS 16.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specification flag register (PR0L, PR0H, PR1L) •...
Page 324 CHAPTER 16 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input.
Page 325 CHAPTER 16 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, and MK1L can be set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form 16-bit register MK0, they can be set by a 16-bit memory manipulation instruction.
Page 326 CHAPTER 16 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, and PR1L can be set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they can be set by a 16-bit memory manipulation instruction.
Page 327 CHAPTER 16 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP6. EGP and EGN can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 328 CHAPTER 16 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
Page 329 CHAPTER 16 INTERRUPT FUNCTIONS 16.4 Interrupt Servicing Operations 16.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 330 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 331 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 16-9.
Page 332 CHAPTER 16 INTERRUPT FUNCTIONS 16.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment.
Page 333 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 334 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 1 IE = 0...
Page 335 CHAPTER 16 INTERRUPT FUNCTIONS 16.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 336 CHAPTER 17 KEY INTERRUPT FUNCTION 17.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 17-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0...
Page 337 CHAPTER 17 KEY INTERRUPT FUNCTION 17.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears KRM to 00H.
Page 338 CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function and Configuration 18.1.1 Standby function Table 18-1. Relationship Between Operation Clocks in Each Operation Status High-Speed System Ring-OSC Oscillator Subsystem CPU Clock Prescaler Clock Status Clock Oscillator Clock After Supplied to Peripherals Oscillator Release MSTOP = 0 MSTOP = 1...
Page 339 CHAPTER 18 STANDBY FUNCTION In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1.
Page 340 CHAPTER 18 STANDBY FUNCTION 18.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, refer to CHAPTER 5 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the high-speed system clock oscillation stabilization time counter.
Page 341 CHAPTER 18 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the high-speed system clock oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the high-speed system clock is selected as the CPU clock.
Page 342 CHAPTER 18 STANDBY FUNCTION 18.2 Standby Function Operation 18.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, Ring-OSC clock, or subsystem clock. The operating statuses in the HALT mode are shown below.
Page 343 CHAPTER 18 STANDBY FUNCTION Table 18-2. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When High-Speed System Clock When High-Speed System Clock Oscillation Continues Oscillation Stopped Item When Ring-OSC When Ring-OSC When Ring-OSC...
Page 344 CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 345 CHAPTER 18 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-4.
Page 346 CHAPTER 18 STANDBY FUNCTION Figure 18-4. HALT Mode Release by RESET Input (2/2) (3) When subsystem clock is used as CPU clock HALT instruction RESET signal Operating Reset Operation Status of CPU mode period stopped HALT mode Operating mode (17/f (Ring-OSC clock) Subsystem clock...
Page 347 CHAPTER 18 STANDBY FUNCTION 18.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set when the CPU clock before the setting was the high-speed system clock or Ring-OSC clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
Page 348 CHAPTER 18 STANDBY FUNCTION (2) STOP mode release Figure 18-5. Operation Timing When STOP Mode Is Released STOP mode release STOP mode High-speed system clock Ring-OSC clock High-speed system clock is selected as CPU clock HALT status High-speed system clock when STOP instruction (oscillation stabilization time set by OSTS) is executed...
Page 349 CHAPTER 18 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 18-6.
Page 350 CHAPTER 18 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 18-7. STOP Mode Release by RESET Input (1) When high-speed system clock is used as CPU clock STOP instruction...
Page 351 CHAPTER 19 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor high-speed system clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 352 Figure 19-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF CLMRF LVIRF Watchdog timer reset signal Clear Clear Clear Clock monitor reset signal Reset signal RESET Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit.
Page 353 CHAPTER 19 RESET FUNCTION Figure 19-2. Timing of Reset by RESET Input Ring-OSC clock High-speed system clock Operation stop Normal operation Reset period CPU clock Normal operation (17/f (Reset processing, Ring-OSC clock) (Oscillation stop) RESET Internal reset signal Delay Delay Port pin Hi-Z (except P130)
Page 354 CHAPTER 19 RESET FUNCTION Figure 19-4. Timing of Reset in STOP Mode by RESET Input Ring-OSC clock High-speed system clock STOP instruction execution Operation stop Normal Normal operation Reset period Stop status CPU clock (17/f operation (Reset processing, Ring-OSC clock) (Oscillation stop) (Oscillation stop) RESET...
Page 355 CHAPTER 19 RESET FUNCTION Table 19-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Status After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
Page 356 CHAPTER 19 RESET FUNCTION Table 19-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Status After Reset Acknowledgment A/D converter Conversion result register (ADCR) Undefined Mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) Serial interface UART0 Receive buffer register 0 (RXB0) Transmit shift register 0 (TXS0)
Page 357 CHAPTER 19 RESET FUNCTION 19.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KD1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Page 358 CHAPTER 20 CLOCK MONITOR 20.1 Functions of Clock Monitor The clock monitor samples the high-speed system clock using the on-chip Ring-OSC, and generates an internal reset signal when the high-speed system clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1.
Page 359 CHAPTER 20 CLOCK MONITOR 20.3 Register Controlling Clock Monitor The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CLM to 00H.
Page 360 CHAPTER 20 CLOCK MONITOR 20.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows. <Monitor start condition> When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1). <Monitor stop condition>...
Page 361 CHAPTER 20 CLOCK MONITOR Figure 20-3. Timing of Clock Monitor (1/4) (1) When internal reset is executed by oscillation stop of high-speed system clock 4 clocks of Ring-OSC clock High-speed system clock Ring-OSC clock Internal reset signal CLME CLMRF (2) Clock monitor status after RESET input (CLME = 1 is set after RESET input and during high-speed system clock oscillation stabilization time) Clock supply Normal...
Page 362 CHAPTER 20 CLOCK MONITOR Figure 20-3. Timing of Clock Monitor (2/4) (3) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of high-speed system clock oscillation stabilization time) Normal Clock supply operation CPU operation Reset...
Page 363 CHAPTER 20 CLOCK MONITOR Figure 20-3. Timing of Clock Monitor (3/4) (5) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode) Clock supply Normal stopped Normal operation operation...
Page 364 CHAPTER 20 CLOCK MONITOR Figure 20-3. Timing of Clock Monitor (4/4) (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software Normal operation (high-speed system clock or subsystem clock) CPU operation High-speed system clock Ring-OSC clock Oscillation stopped Note RSTOP CLME...
Page 365 CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V = 2.1 V ±0.1 V Note ) and detection voltage (V ), and generates internal reset signal when V <...
Page 366 CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Detection voltage source 21.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (V ) and detection voltage (V ) are compared, and when V...
Page 367 CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 368 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-3. Example of Software Processing After Release of Reset (2/2) • Checking cause of reset Check cause of reset WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF...
Page 369 CHAPTER 22 LOW-VOLTAGE DETECTOR 22.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has the following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V <...
Page 370 CHAPTER 22 LOW-VOLTAGE DETECTOR 22.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 371 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 22-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H Symbol...
Page 372 CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when <...
Page 373 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (V LVI detection voltage POC detection voltage Time <2> LVIMK flag (set by software) Note 1 <1> LVION flag Not cleared Not cleared (set by software) <3>...
Page 374 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS).
Page 375 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (V LVI detection voltage POC detection voltage Time <2> LVIMK flag (set by software) Note 1 <1> <7> Cleared by software LVION flag (set by software) <3>...
Page 376 CHAPTER 22 LOW-VOLTAGE DETECTOR 22.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
Page 377 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
Page 378 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-6. Example of Software Processing After Release of Reset (2/2) • Checking cause of reset Check cause of reset WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF...
Page 379 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When used as interrupt Check that “supply voltage (V ) > detection voltage (V )” in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L) to 0 and enable interrupts (EI).
Page 380 CHAPTER 23 OPTION BYTE The 78K0/KD1+ has an area called an option byte at address 0080H of the flash memory. When using the product, be sure to set the following functions by using the option byte. ○ Ring-OSC oscillation • Cannot be stopped. •...
Page 381 CHAPTER 24 FLASH MEMORY µ µ PD78F0122H, 78F0123H, and 78F0124H/HD replace the internal mask ROM of the PD780122, 780123, and 780124 of the 78K0/KD1 respectively with flash memory to which a program can be written, erased, and overwritten while mounted on the board. Table 24-1 lists the differences between the 78K0/KD1+ and the 78K0/KD1. Table 24-1.
Page 382 CHAPTER 24 FLASH MEMORY 24.1 Internal Memory Size Switching Register The internal memory capacity can be selected using the internal memory size switching register (IMS). IMS can be set by an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Caution Be sure to set each product to the values shown in Table 24-2 at initialization.
Page 383 CHAPTER 24 FLASH MEMORY 24.2 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0/KD1+ has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system.
Page 384 CHAPTER 24 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 24-2. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode (2.7 to 5.5 V) LVDD (VDD2) 52 51 50 49 48 47 46 45 44 43 42 41 40...
Page 385 CHAPTER 24 FLASH MEMORY Figure 24-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode (2.7 to 5.5 V) LVDD (VDD2) 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 21 23 24 25 26 /RESET FLMD0 FLMD1 HS...
Page 386 CHAPTER 24 FLASH MEMORY Figure 24-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode (2.7 to 5.5 V) LVDD (VDD2) 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 21 23 24 25 26 /RESET FLMD0 FLMD1 HS WRITER INTERFACE...
Page 387 CHAPTER 24 FLASH MEMORY 24.3 Programming Environment The environment required for writing a program to the flash memory of the 78K0/KD1+ is illustrated below. Figure 24-5. Environment for Writing Program to Flash Memory FLMD0 FLMD1 RS-232C Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 RESET 78K0/KD1+...
Page 388 CHAPTER 24 FLASH MEMORY 24.4 Communication Mode Communication between the dedicated flash programmer and the 78K0/KD1+ is established by serial communication via CSI10 or UART6 of the 78K0/KD1+. (1) CSI10 Transfer rate: 200 kHz to 2 MHz Figure 24-6. Communication with Dedicated Flash Programmer (CSI10) FLMD0 FLMD0 FLMD1...
Page 389 CHAPTER 24 FLASH MEMORY (3) UART6 Transfer rate: 4800 to 76800 bps Figure 24-8. Communication with Dedicated Flash Programmer (UART6) FLMD0 FLMD0 FLMD1 FLMD1 Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 /RESET RESET SI/RxD TxD6 Dedicated flash 78K0/KD1+ programmer SO/TxD RxD6 If Flashpro IV is used as the dedicated flash programmer, Flashpro IV generates the following signal for the 78K0/KD1+.
Page 390 CHAPTER 24 FLASH MEMORY 24.5 Handling of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 391 CHAPTER 24 FLASH MEMORY 24.5.3 Serial interface pins The pins used by each serial interface are listed below. Table 24-5. Pins Used by Each Serial Interface Serial Interface Pins Used CSI10 SO10, SI10, SCK10 CSI10 + HS SO10, SI10, SCK10, HS/P15 UART6 TxD6, RxD6 To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on...
Page 392 CHAPTER 24 FLASH MEMORY (2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction.
Page 393 CHAPTER 24 FLASH MEMORY 24.5.5 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to V or V via a resistor.
Page 394 CHAPTER 24 FLASH MEMORY 24.6 Programming Method 24.6.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 24-14. Flash Memory Manipulation Procedure Start Flash memory programming FLMD0 pulse supply mode is set Selecting communication mode Manipulate flash memory End? Preliminary User’s Manual U16962EJ1V0UD...
Page 395 CHAPTER 24 FLASH MEMORY 24.6.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0/KD1+ in the flash memory programming mode. To set the mode, set the FLMD0 pin to V and clear the reset signal.
Page 396 CHAPTER 24 FLASH MEMORY 24.6.3 Selecting communication mode In the 78K0/KD1+, a communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin after the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash programmer.
Page 397 CHAPTER 24 FLASH MEMORY 24.6.4 Communication commands The 78K0/KD1+ communicates with the dedicated flash programmer by using commands. The signals sent from the flash programmer to the 78K0/KD1+ are called commands, and the commands sent from the 78K0/KD1+ to the dedicated flash programmer are called response commands.
Page 398 CHAPTER 24 FLASH MEMORY 24.7 Flash Memory Programming by Self-Writing The 78K0/KD1+ supports a self-programming function that can be used to rewrite the flash memory via a user program, so that the program can be upgraded in the field. The programming mode is selected by bits 0 and 1 (FLSPM0 and FLSPM1) of the flash programming mode control register (FLPMC).
Page 399 CHAPTER 24 FLASH MEMORY 24.7.1 Registers used for self-programming function The following three registers are used for the self-programming function. • Flash programming mode control register (FLPMC) • Flash protect command register (PFCMD) • Flash status register (PFS) (1) Flash programming mode control register (FLPMC) This register is used to enable or disable writing or erasing of the flash memory and to set the operation mode during self-programming.
Page 400 CHAPTER 24 FLASH MEMORY Figure 24-18. Format of Flash Programming Mode Control Register (FLPMC) Note 1 Note 2 Address: FFC4H After reset: 0×H Symbol FLPMC FWEDIS FWEPR FLSPM1 FLSPM0 FWEDIS Control of flash memory writing/erasing Note 3 Writing/erasing enabled Writing/erasing disabled FWEPR Status of FLMD0 pin Low level...
Page 401 CHAPTER 24 FLASH MEMORY (2) Flash protect command register (PFCMD) If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system.
Page 402 CHAPTER 24 FLASH MEMORY (3) Flash status register (PFS) If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error occurs.
Page 403 CHAPTER 24 FLASH MEMORY 24.8 Boot Swap Function The 78K0/KD1+ has a boot swap function. Even if a momentary power failure occurs for some reason while the boot area is being rewritten by self- programming and the program in the boot area is lost, the boot swap function can execute the program correctly after re-application of power, reset, and start.
Page 404 CHAPTER 24 FLASH MEMORY 24.8.2 Memory map and boot area Figure 24-22 shows the memory map and boot area. The boot program area of the 78K0/KD1+ is in 4 KB units. When boot swap is executed, boot cluster 0 and boot cluster 1 in the figure are exchanged. Figure 24-22.
Page 405 CHAPTER 24 FLASH MEMORY Figure 24-22. Memory Map and Boot Area (2/4) µ PD78F0123H F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H General-purpose registers 32 × 8 bits F E E 0 H F E D F H Internal high-speed RAM...
Page 406 CHAPTER 24 FLASH MEMORY Figure 24-22. Memory Map and Boot Area (3/4) µ PD78F0124H F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H General-purpose registers 32 × 8 bits F E E 0 H F E D F H Internal high-speed RAM...
Page 407 CHAPTER 24 FLASH MEMORY Figure 24-22. Memory Map and Boot Area (4/4) µ PD78F0124HD FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits Note 1 FB00H FAFFH...
Page 408 µ CHAPTER 25 ON-CHIP DEBUG FUNCTION ( PD78F0124HD ONLY) µ PD78F0124HD uses the V , FLMD0, RESET, X1 (or P31), X2 (or P32), and V pins to communicate with the host machine via an in-circuit emulator (IECUBE for 78K0/Kx1+ (provisional name)) for on-chip debugging. Whether X1 and P31, or X2 and P32 are used can be selected.
Page 409 CHAPTER 26 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KD1+ in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 26.1 Conventions Used in Operation List 26.1.1 Operand identifiers and specification methods Operands are written in the “Operand”...
Page 410 CHAPTER 26 INSTRUCTION SET 26.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 411 CHAPTER 26 INSTRUCTION SET 26.2 Operation List Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Z AC CY Note 1 Note 2 − r ← byte 8-bit data r, #byte transfer (saddr) ← byte saddr, #byte − sfr ← byte sfr, #byte −...
Page 412 CHAPTER 26 INSTRUCTION SET Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word transfer (saddrp) ← word saddrp, #word − sfrp ← word sfrp, #word AX ←...
Page 413 CHAPTER 26 INSTRUCTION SET Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte operation (saddr), CY ← (saddr) − byte × ×...
Page 414 CHAPTER 26 INSTRUCTION SET Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte operation (saddr) ← (saddr) ∨ byte × saddr, #byte − A ← A ∨ r ×...
Page 415 CHAPTER 26 INSTRUCTION SET Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation AX, CY ← AX − word −...
Page 416 CHAPTER 26 INSTRUCTION SET Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Z AC CY Note 1 Note 2 CY ← CY ∧ (saddr.bit) × AND1 CY, saddr.bit manipulate CY ← CY ∧ sfr.bit − × CY, sfr.bit − CY ← CY ∧ A.bit ×...
Page 417 CHAPTER 26 INSTRUCTION SET Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ← addr16, SP ← SP − 2 −...
Page 418 CHAPTER 26 INSTRUCTION SET Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Conditional saddr.bit, $addr16 branch PC ← PC + 4 + jdisp8 if sfr.bit = 1 −...
Page 419 CHAPTER 26 INSTRUCTION SET 26.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand #byte saddr !addr16 [DE]...
Page 420 CHAPTER 26 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 421 CHAPTER 26 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand CALL Basic instruction CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U16962EJ1V0UD...
Page 422 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) Caution These specifications show target values, which may change after device evaluation. operating voltage range may also change. Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +6.5 −0.3 to +0.3 −0.3 to +0.3 −0.3 to V...
Page 423 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) High-Speed System Clock (Crystal/Ceramic) Oscillator Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN.
Page 424 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) Ring-OSC Oscillator Characteristics = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V, 2.0 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Parameter Conditions MIN. TYP. MAX. Unit On-chip Ring-OSC oscillator Oscillation frequency (f...
Page 425 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (1/3) = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V , 2.0 V ≤ AV ≤ V Note 1 Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 426 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (2/3) = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V , 2.0 V ≤ AV ≤ V Note 1 Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 427 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (3/3) = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V , 2.0 V ≤ AV ≤ V Note 1 Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 428 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) AC Characteristics (1) Basic operation = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V, 2.0 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP.
Page 429 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) 20.0 16.0 10.0 4.17 Guaranteed operation range 0.238 0.125 2.7 3.3 Supply voltage V Remark The values indicated by the shaded section are only when the Ring-OSC clock is selected. Preliminary User’s Manual U16962EJ1V0UD...
Page 430 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) (2) Serial interface = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions...
Page 431 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) AC Timing Test Points (Excluding X1, XT1) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) (MAX.) (MIN.) (MAX.) TI Timing TIL0 TIH0 TI000, TI010 TIL5 TIH5 TI50, TI51 Interrupt Request Input Timing INTL INTH INTP0 to INTP6 Preliminary User’s Manual U16962EJ1V0UD...
Page 432 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK10 SIKm KSIm SI10 Input data KSOm SO10 Output data Remark m = 1, 2 Preliminary User’s Manual U16962EJ1V0UD...
Page 433 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) A/D Converter Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 4.0 V ≤...
Page 434 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage LVI0 LVI1 LVI2 LVI3 LVI4 3.15 3.45 LVI5 2.95 3.25 LVI6 2.85 LVI7 LVI8 2.25 2.35 2.45 LVI9 Note 1 Response time Minimum pulse width...
Page 435 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET) Flash Memory Programming Characteristics = +10 to +65°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = 0 V) (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit supply voltage = 10 MHz, V = 5.5 V T.B.D.
Page 436 CHAPTER 28 PACKAGE DRAWING 52-PIN PLASTIC LQFP (10x10) detail of lead end ITEM MILLIMETERS 12.0±0.2 10.0±0.2 10.0±0.2 12.0±0.2 0.32±0.06 0.13 0.65 (T.P.) 1.0±0.2 0.17 +0.03 −0.05 0.10 0.1±0.05 3° +4° −3° 1.5±0.1 0.25 0.6±0.15 S52GB-65-8ET-2 Preliminary User’s Manual U16962EJ1V0UD...
Page 437 CHAPTER 29 CAUTIONS FOR WAIT 29.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
Page 438 CHAPTER 29 CAUTIONS FOR WAIT 29.2 Peripheral Hardware That Generates Wait Table 29-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 29-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Register Access...
Page 439 CHAPTER 29 CAUTIONS FOR WAIT 29.3 Example of Wait Occurrence <1> Watchdog timer <On execution of MOV WDTM, A> Number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).) <On execution of MOV WDTM, #byte>...
Page 440 Unless otherwise specified, “Windows” means the following OSs. • Windows 3.1 • Windows 95 • Windows 98 • Windows NT Ver. 4.0 • Windows 2000 • Windows XP Caution For the development tools of the 78K0/KD1+, contact an NEC Electronics sales representative. Preliminary User’s Manual U16962EJ1V0UD...
Page 441 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/3) (1) When using the in-circuit emulators IE-78K0-NS, IE-78K0-NS-A Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package • System simulator •...
Page 442 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/3) (2) When using the in-circuit emulator IE-78K0K1-ET Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package • System simulator •...
Page 443 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (3/3) Note 1 (3) When using the in-circuit emulator IECUBE for 78K0/Kx1+ (provisional name) Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package •...
Page 444 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package µ Part number: S××××SP78K0 Remark ×××× in the part number differs depending on the host machine and OS used. µ...
Page 445 APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 ×××× Host Machine Supply Medium AB13 PC-9800 series, Windows (Japanese version) 3.5-inch 2HD FD IBM PC/AT compatibles BB13 Windows (English version) AB17...
Page 446 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A Caution The oscillation frequency is up to 10 MHz when the IE-78K0-NS or IE-78K0-NS-A is used. IE-78K0-NS The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K/0 Series product.
Page 447 APPENDIX A DEVELOPMENT TOOLS A.5.2 When using in-circuit emulator IE-78K0K1-ET Caution The oscillation frequency is up to 10 MHz when the IE-78K0K1-ET is used. Note IE-78K0K1-ET The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K0/Kx1 or 78K0/Kx1+ product. It corresponds to the integrated debugger (ID78K0-NS).
Page 448 APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) SM78K0 This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based System simulator software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine.
Page 449 APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the emulation probe and conversion adapter. Design your system making allowances for conditions such as the shape of parts mounted on the target system, as shown below.
Page 450 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Conditions of Target System Emulation board (part number pending) Emulation probe NP-H52GB-TQ 22 mm Conversion 11 mm adapter TGB-052SBP 16.45 mm 16.45 mm 42 mm 45 mm Target system Remark The NP-H52GB-TQ is a product of Naito Densei Machida Mfg.
Page 451 APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register (ADCR) ........................229 A/D converter mode register (ADM)..........................226 Analog input channel specification register (ADS) ......................228 Asynchronous serial interface control register 6 (ASICL6)..................278 Asynchronous serial interface operation mode register 0 (ASIM0) ................248 Asynchronous serial interface operation mode register 6 (ASIM6) ................272 Asynchronous serial interface reception error status register 0 (ASIS0)..............250...
Page 452 APPENDIX C REGISTER INDEX Input switch control register (ISC) ..........................280 Internal memory size switching register (IMS)......................382 Interrupt mask flag register 0H (MK0H)........................325 Interrupt mask flag register 0L (MK0L) ........................325 Interrupt mask flag register 1L (MK1L) ........................325 Interrupt request flag register 0H (IF0H) ........................324 Interrupt request flag register 0L (IF0L)........................324 Interrupt request flag register 1L (IF1L)........................324 Key return mode register (KRM) ..........................337...
Page 453 APPENDIX C REGISTER INDEX Processor clock control register (PCC) .........................97 Pull-up resistor option register 0 (PU0) .........................93 Pull-up resistor option register 1 (PU1) .........................93 Pull-up resistor option register 12 (PU12) ........................93 Pull-up resistor option register 14 (PU14) ........................93 Pull-up resistor option register 3 (PU3) .........................93 Pull-up resistor option register 7 (PU7) .........................93 Receive buffer register 0 (RXB0) ..........................247 Receive buffer register 6 (RXB6) ..........................271...
Page 454 APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR: A/D conversion result register .........................229 ADM: A/D converter mode register........................226 ADS: Analog input channel specification register .....................228 ASICL6: Asynchronous serial interface control register 6 ..................278 ASIF6: Asynchronous serial interface transmission status register 6 ..............275 ASIM0:...
Page 455 APPENDIX C REGISTER INDEX LVIM: Low-voltage detection register ........................370 LVIS: Low-voltage detection level selection register ..................371 MCM: Main clock mode register ........................100 MK0H: Interrupt mask flag register 0H ........................325 MK0L: Interrupt mask flag register 0L.........................325 MK1L: Interrupt mask flag register 1L.........................325 MOC: Main OSC control register ........................101 OSTC:...
Page 456 APPENDIX C REGISTER INDEX RCM: Ring-OSC mode register ...........................99 RESF: Reset control flag register........................357 RXB0: Receive buffer register 0 .........................247 RXB6: Receive buffer register 6 .........................271 SIO10: Serial I/O shift register 10 ........................305 SOTB10: Transmit buffer register 10 ........................305 TCL50: Timer clock selection register 50 ......................163 TCL51: Timer clock selection register 51 ......................163...

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NEC 78K0/KD1+ Preliminary User's Manual

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