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Hitachi HDS725050KLA360 Specifications
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Hitachi HDS725050KLA360 Specifications

3.5 inch ultra ata/133 hard disk drive, 3.5 inch serial ata hard disk drive
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Hard Disk Drive Specification
Deskstar 7K500
Deskstar E7K500
3.5 inch Ultra ATA/133 hard disk drive
3.5 inch Serial ATA hard disk drive
Models:
HDS725050KLAT80
HDS725050KLA360
Version 1.5
12 September 2006

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  • Page 1 Hard Disk Drive Specification Deskstar 7K500 Deskstar E7K500 3.5 inch Ultra ATA/133 hard disk drive 3.5 inch Serial ATA hard disk drive Models: HDS725050KLAT80 HDS725050KLA360 Version 1.5 12 September 2006...
  • Page 3 Hard Disk Drive Specification Deskstar 7K500 Deskstar E7K500 3.5 inch Ultra ATA/133 hard disk drive 3.5 inch Ultra Serial/ATA hard disk drive Models: HDS725050KLAT80 HDS725050KLA360 Version 1.5 12 September 2006...
  • Page 4 It is possible that this publication may contain reference to, or information about, Hitachi products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Hitachi intends to announce such Hitachi products, programming, or services in your coun- try.

  • Page 5: Table Of Contents

    Table of Contents 1.0 General......................1 1.1 Introduction.....................1 1.2 References....................1 1.3 Abbreviations..................1 1.4 Caution....................3 2.0 General features of the drive ................5 3.0 Fixed-disk subsystem description..............9 3.1 Control electronics ..................9 3.2 Head disk assembly ................9 3.3 Actuator ....................9 4.0 Drive characteristics ..................11 4.1 Default logical drive parameters.............11 4.2 Data sheet....................12 4.3 World Wide Name Assignment ..............12...
  • Page 6 6.8.2 Host Pausing Read DMA..............36 6.8.3 Host Terminating Read DMA............37 6.8.4 Device Terminating Read DMA.............38 6.8.5 Initiating Write DMA ..............39 6.8.6 Device Pausing Write DMA ............40 6.8.7 Device Terminating Write DMA ............41 6.8.8 Host Terminating Write DMA............42 6.9 Addressing of registers ................43 6.9.1 Cabling....................43 7.0 Jumper Settings (PATA model)..............45 7.1 Connector location ..................45...
  • Page 7 7.9.4 Safe handling ..................62 7.9.5 Environment..................62 7.9.6 Secondary circuit protection ............62 7.10 Electromagnetic compatibility ..............63 7.10.1 CE mark ..................63 7.10.2 C-TICK mark ................63 7.10.3 BSMI mark ...................63 7.11 Packaging....................63 8.0 General......................65 8.1 Introduction.....................65 8.2 Terminology....................65 8.3 Deviations from standard................65 9.0 Registers......................67 9.1 Register set....................67 9.2 Alternate Status Register ................68 9.3 Command Register .................68...
  • Page 8 10.6.7 Error log ..................82 10.6.8 Self-test ..................82 10.7 Security Mode Feature Set..............83 10.7.1 Security mode ................83 10.7.2 Security level ................83 10.7.3 Passwords..................84 10.7.4 Operation example ................84 10.7.5 Command table ................87 10.8 Host Protected Area Feature ..............88 10.8.1 Example for operation (In LBA Mode) ........88 10.8.2 Security extensions ...............89 10.9 Seek overlap..................90 10.10 Write cache function ................91...
  • Page 9 12.5 Execute Device Diagnostic (90h) ............119 12.6 Flush Cache (E7h) ................120 12.7 Flush Cache Ext (EAh) .................121 12.8 Format Track (50h) ................122 12.9 Format Unit (F7h) .................123 12.10 Identify Device (ECh).................124 12.11 Idle (E3h/97h) ..................135 12.12 Idle Immediate (E1h/95h) ..............136 12.13 Initialize Device Parameters (91h) .............137 12.14 Read Buffer (E4h)................138 12.15 Read DMA (C8h/C9h)................139...
  • Page 10 12.38.2 Set Max Lock (Feature=02h)............192 12.38.3 Set Max Unlock (Feature = 03h) ..........193 12.38.4 Set Max Freeze Lock (Feature = 04h) ........194 12.39 Set Max Address Ext (37h)..............195 12.40 Set Multiple (C6h) ................197 12.41 Sleep (E6h/99h) ..................198 12.42 S.M.A.R.T. Function Set (B0h) ............199 12.42.1 S.M.A.R.T.
  • Page 11 List of Tables Table 1. Formatted capacity................11 Table 2. Mechanical positioning performance ..........12 Table 3. World Wide Name Assignment............12 Table 4. Command overhead .................14 Table 5. Mechanical positioning performance ..........15 Table 6. Full stroke seek time ................15 Table 7. Single Track Seek Time..............16 Table 8.
  • Page 12 Table 44. Temperature and humidity.............50 Table 45. Limits of temperature and humidity ..........50 Table 46. Input voltage ..................51 Table 47. Power supply current of PATA model ..........51 Table 48. Power supply current of SATA model ..........52 Table 49. Power supply generated ripple at drive power connector....52 Table 50.
  • Page 13 Table 90. Identify device information (Part 3 of 7) ........127 Table 91. Identify device information (Part 4 of 7) ........128 Table 92. Identify device information (Part 5 of 7 ........130 Table 93. Identify device information (Part 6 of 7) ........132 Table 94.
  • Page 14 Table 136. Security Unlock command (F2h)..........183 Table 137. Seek command (7xh) ..............184 Table 138. Set Features command (EFh)............185 Table 139. Set Max ADDRESS command (F9h) ..........189 Table 140. Set Max Set Password command..........191 Table 141. Set Max Set Password data contents ...........191 Table 142.

  • Page 15: General

    This document describes the specifications of the Deskstar 7K500 and Deskstar E7K500, a 3.5-inch, 7200-rpm hard disk drive with the following model numbers: • Deskstar 7K500 - HDS725050KLAT80 (500 GB/PATA) • Deskstar E7K500 - HDS725050KLA360 (500 GB/SATA*) *Please note default setting is 1.5Gbps. These specifications are subject to change without notice.
  • Page 16 (32 ft/sec) per Hertz 1,000,000,000 bits 1,000,000,000 bytes ground hexadecimal hard disk drive Hertz Input integrated lead suspension Input/Output International Standards Organization 1,000 bytes Kbpi 1000 bits per inch kgf-cm kilogram (force)-centimeter kilohertz logical block addressing unit of A-weighted sound power meter maximum 1,000,000 bytes...

  • Page 17: Caution

    reset read/write second SELV secondary low voltage S.M.A.R.T Self-Monitoring, Analysis, and Reporting Technology tracks per inch track transistor-transistor logic Underwriters Laboratory volt Verband Deutscher Electrotechniker watt 3-state transistor-transistor tristate logic 1.4 Caution • Do not apply force to the top cover. •...
  • Page 18 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 19: General Features Of The Drive

    2.0 General features of the drive • Formatted capacities of 500 GB • Spindle speeds of 7200 RPM • Fluid Dynamic Bearing motor • Enhanced IDE interface / Serial ATA interface • Sector format of 512 bytes/sector • Closed-loop actuator servo •...
  • Page 20 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...
  • Page 21 Part 1. Functional specification Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive specification...
  • Page 22 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 23: Fixed-Disk Subsystem Description

    3.0 Fixed-disk subsystem description 3.1 Control electronics The drive is electronically controlled by a microprocessor, several logic modules, digital/analog modules, and var- ious drivers and receivers. The control electronics performs the following major functions: • Controls and interprets all interface signals between the host controller and the drive. •...
  • Page 24 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 25: Drive Characteristics

    4.0 Drive characteristics 4.1 Default logical drive parameters Table 1: Formatted capacity HDS725050KLXXXX Physical Layout Label capacity (GB) Bytes per sector Sectors per track 594-1242 Number of heads Number of disks Data sectors per cylinder 5940-12420 Data cylinders per zone 2000 - 4500 Logical layout Number of heads...

  • Page 26: Data Sheet

    Number of data bands Upper 271 KB is used for firmware 4.3 World Wide Name Assignment Table 3: World Wide Name Assignment Description Organization Hitachi Global Storage Technologies Manufacturing Site Prachiburi, Thailand Product Deskstar 7K500 and Deskstar E7K500 000CCAh SHBU Block Assignment...

  • Page 27: Cylinder Allocation

    This cylinder contains the user data which can be sent and retrieved via read/write commands and a spare area for reassigned data. Spare cylinder The spare cylinder is used by Hitachi Global Storage Technologies manufacturing and includes data sent from a defect loca- tion. 4.4 Performance characteristics Drive performance is characterized by the following parameters: •...

  • Page 28: Command Overhead

    Latency • Data transfer speed • Buffering operation (Look ahead/Write cache) All the above parameters contribute to drive performance. There are other parameters that contribute to the performance of the actual system. This specification tries to define the bare drive characteristics, not system throughput, which depends on the system and the application.

  • Page 29: Mechanical Positioning

    4.4.2 Mechanical positioning 4.4.2.1 Average seek time (including settling) Table 5: Mechanical positioning performance Command type Typical (ms) Max (ms) Read Write 10.2 Read (Quiet Seek mode) 19.5 20.5 Write (Quiet Seek mode) 20.5 21.5 The terms “Typical” and “Max” are used throughout this document and are defined as follows: Typical The average of the drive population tested at nominal environmental and voltage conditions.

  • Page 30: Drive Ready Time

    4.4.2.3 Head switch time (head skew) Head switch time-typical (ms) Head switch time is defined as the amount of time required by the fixed disk to complete a seek of the next sequential track after reading the last sector in the current track 4.4.2.4 Cylinder switch time (cylinder skew) Head switch time-typical (ms) Cylinder switch time is defined as the amount of time required by the fixed disk to access the next sequential block after read-...

  • Page 31: Data Transfer Speed

    4.4.4 Data transfer speed Table 10: Data transfer speed Data transfer speed (Mbytes/sec) Disk-Buffer transfer (Zone 0) Instantaneous - typical 76.3 MB/s Sustained - read typical 64.8 MB/s Disk-Buffer transfer (Zone 29) Instantaneous - typical 36.5 MB/s Sustained - read typical 31.0 MB/s Buffer - host (max) 133 (PATA), 300(SATA)

  • Page 32: Throughput

    4.4.5 Throughput 4.4.5.1 Simple sequential access The following table illustrates simple sequential access for the enclosure. Table 11: Simple Sequential Access performance Operation Typical (sec) Max (sec) Sequential Read (Zone 0) 0.29 0.30 Sequential Read (Zone 29) 0.59 0.61 The above table gives the time required to read a total of 8000h consecutive blocks (16,777,216 bytes) accessed by 128 read commands.

  • Page 33: Operating Modes

    4.4.6 Operating modes 4.4.6.1 Description of operating modes Table 13: Description of operating modes Operating mode Description Start up time period from spindle stop or power down. Spin-up Seek operation mode Seek Write operation mode Write Read operation mode Read Spindle rotation at 7200 RPM with heads unloaded.
  • Page 34 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 35: Defect Flagging Strategy

    5.0 Defect flagging strategy Media defects are remapped to the next available sector during the Format Process in manufacturing. The mapping from LBA to the physical locations is calculated by an internally maintained table. Shipped format • Data areas are optimally used. •...
  • Page 36 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 37: Specification

    6.0 Specification 6.1 Electrical Interface 6.1.1 Connector location Refer to the following illustration to see the location of the connectors: PATA Model SATA Model Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 38: 4Pin Dc Power Connector

    6.1.2 4pin DC Power connector The 4pin DC power connector is designed to mate with AMP part number 1-480424-0 using AMP pins part num- ber 350078-4 (strip), part number 61173-4 (loose piece), or their equivalents. Pin assignments are shown in the fig- ure below.

  • Page 39: Signal Definitions (Pata Model)

    6.2 Signal definitions (PATA model) The pin assignments of interface signals are listed as follows: Table 16: Signal definitions SIGNAL Type SIGNAL Type RESET- 3–state DD08 3–state 3–state DD09 3–state 3–state DD10 3–state 3–state DD11 3–state 3–state DD12 3–state 3–state DD13 3–state 3–state...

  • Page 40: Signal Descriptions

    6.3 Signal descriptions Table 17: Special signal definitions for Ultra DMA Special Definition Conventional (for Ultra DMA) Definition DDMARDY- IORDY Write Operation HSTROBE DIOR- STOP DIOW- HDMARDY- DIOR- Read Operation DSTROBE IORDY STOP DIOW- DD00–DD15 A 16-bit bi-directional data bus between the host and the drive. The lower 8 lines, DD00-07, are used for Regis- ter and ECC access.
  • Page 41 DASP- This is a time-multiplexed signal which indicates that a drive is active or that device 1 is present. This signal is driven by an Open-Drain driver and internally pulled up to 5 volts through a 10 kW resistor. During a Power-On initialization or after RESET- is negated, DASP- shall be asserted by Device 1 within 400 ms to indicate that device 1 is present.
  • Page 42 DMACK- This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted, or that data is available. This signal is internally pulled up to 5 Volt through a 15kΩ resistor with a resistor tolerance value of –50% to +100%.

  • Page 43: Interface Logic Signal Levels (Pata Model)

    6.4 Interface logic signal levels (PATA model) The interface logic signals have the following electrical specifications: Input High Voltage 2.0 V min Inputs Input Low Voltage 0.8 V max. Output High Voltage 2.4 V min. Outputs: Output Low Voltage 0.5 V max. 6.4.1 Signal definition (SATA model) SATA has receivers and drivers to be connected to Tx+/ - and Rx +/- Serial data signal defines the signal names of I/O connec- tor pin and signal name.

  • Page 44: Out Of Band Signaling (Sata Model)

    6.4.1.1 TX+ / TX These signal are the outbound high-speed differential signals that are connected to the serial ATA cable. 6.4.1.2 RX+ / RX These signals are the inbound high-speed differential signals that are connected to the serial ATA cable. The following standard shall be referenced about signal specifications.

  • Page 45: Signal Timings (Pata Model)

    6.5 Signal timings (PATA model) 6.5.1 Reset timings Table 21: System reset timing chart RESET- BUSY PARAMETER DESCRIPTION Min (µs) Max (µs) RESET low width RESET high to not BUSY Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 46: Pio Timings

    6.6 PIO timings The PIO cycle timings meet Mode 4 of the ATA/ATAPI-6 description. Table 22: PIO cycle timings chart CS(1:0)- DA(2:0) DIOR-, DIOW - W rite data DD(15:0) Read data DD(15:0) t7(*) t8(*) IOCS16-(*) IORDY (*) Up to ATA-2 (mode-0,1,2) PARAMETER DESCRIPTION MIN (ns) MAX (ns)

  • Page 47: Read Drq Interval Time

    6.6.2 Read DRQ interval time For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows: • In the event that a host reads the status register only before the sector or block transfer DRQ interval, the DRQ interval 4.2 µs •...

  • Page 48: Multiword Dma Timings

    6.7 Multiword DMA timings The Multiword DMA timings meet Mode 2 of the ATA/ATAPI-6 description. Table 23: Multiword DMA cycle timing chart CS0-/CS1- tLR/tLW DMARQ DMACK- tKR/tKW DIOR-/DIOW- READ DATA WRITE DATA Table 24: Multiword DMA cycle timings PARAMETER DESCRIPTION MIN (ns) MAX (ns) Cycle time...

  • Page 49: Ultra Dma Timings

    6.8 Ultra DMA timings The Ultra DMA timings meet Mode 0, 1, 2, and 4 of the Ultra DMA Protocol. 6.8.1 Initiating Read DMA Table 25: Ultra DMA cycle timing chart (Initiating Read) DMARQ DMACK- tACK tENV STOP tACK tENV t2CYC HDMARDY- tZIORDY...

  • Page 50: Host Pausing Read Dma

    6.8.2 Host Pausing Read DMA Table 27: Ultra DMA cycle timing chart (Host pausing Read) DMARQ DMACK- STOP HDMARDY- tRFS DSTROBE Table 28: Ultra DMA cycle timings (Host pausing Read) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 PARAMETER DESCRIPTION...

  • Page 51: Host Terminating Read Dma

    6.8.3 Host Terminating Read DMA Table 29: Ultra DMA cycle timing chart (Host terminating Read) DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tRFS tIORDYZ DSTROBE xxxxxxxxxxxxxxxxxx RD Data xxxxxxxxxxx DD(15:0) tZAH Device drives DD Host drives DD Table 30: Ultra DMA cycle timings (Host terminating Read) MODE 0 MODE 1 MODE 2...

  • Page 52: Device Terminating Read Dma

    6.8.4 Device Terminating Read DMA Table 31: Ultra DMA cycle timing chart (Device terminating Read) DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tIORDYZ DSTROBE xxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) tZAH Host drives DD Device drives DD Table 32: Ultra DMA cycle timings (Device Terminating Read) MODE 0 MODE 1 MODE 2...

  • Page 53: Initiating Write Dma

    6.8.5 Initiating Write DMA Table 33: Ultra DMA cycle timing chart (Initiating Write) DMARQ DMACK- tENV tACK STOP tZIORDY t2CYC DDMARDY- tCYC tCYC tACK HSTROBE DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx WT Data WT Data WT Data Host drives DD Table 34: Ultra DMA cycle timings (Initiating Write) MODE 0 MODE 1 MODE 2...

  • Page 54: Device Pausing Write Dma

    6.8.6 Device Pausing Write DMA Table 35: Ultra DMA cycle timing chart (Device Pausing Write) DMARQ DMACK- STOP DDMARDY- tRFS HSTROBE Table 36: Ultra DMA cycle timing chart (Device Pausing Write) PARAMETER MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6...

  • Page 55: Device Terminating Write Dma

    6.8.7 Device Terminating Write DMA Table 37: Ultra DMA cycle timing chart (Device Terminating Write) DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK tRFS HSTROBE xxx WT Data xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD Table 38: Ultra DMA cycle timings (Device terminating Write) PARAMETER MODE 0 MODE 1...

  • Page 56: Host Terminating Write Dma

    6.8.8 Host Terminating Write DMA Table 39: Ultra DMA cycle timing chart (Host Terminating Write) DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK HSTROBE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD Table 40: Ultra DMA cycle timings (Host Terminating Write) PARAMETER MODE 0 MODE 1 MODE 2...

  • Page 57: Addressing Of Registers

    6.9 Addressing of registers The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's I/O space. Two chip select lines (CS0– and CS1–) and three address lines (DA0–2) are used to select one of these registers, while a DIOR–...
  • Page 58 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 59: Jumper Settings (Pata Model)

    7.0 Jumper Settings (PATA model) 7.1 Connector location Jumper pins 7.1.1 Jumper pin identification Pin I Pin A DERA001.prz Pin B Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 60: Jumper Pin Assignment

    7.1.2 Jumper pin assignment There are four jumper settings as shown in the following sections: • 16 logical head default (normal use) • 15logical head default • 32 GB clip • Power up in standby Within each of these four jumper settings the pin assignment selects Device 0, Device 1, Cable Selection, or Device 1 Slave Present as shown in the following figures.

  • Page 61: Jumper Positions

    CS/SP RS V 7.1.3 Jumper positions 7.1.3.1 16 logical head default (normal use) The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device1 (Slave) Present. DEVICE 0 (Master) DEVICE 1 (Slave) CABLE SEL DEVICE 1 (Slave) Present Shipping Default Condition...

  • Page 62: Logical Head Default

    Notes: 1. To enable the CSEL mode (Cable Selection mode) the jumper block must be installed at E-F. In the CSEL mode the drive address is determined by AT interface signal #28 CSEL as follows: • When CSEL is grounded or at a low level, the drive address is 0 (Device 0). •...

  • Page 63: Table 42. Jumper Positions For Capacity Clip To 2Gb/32Gb

    7.1.3.3 Capacity clip to 32GB The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device1 (Slave) Present while setting the drive capacity down to 32 GB for the purpose of compatibility. Table 42: Jumper positions for capacity clip to 2GB/32GB DEVICE 0 (M aster) DEVICE 1...
  • Page 64 Notes: 1. These jumper settings are used for limiting power supply current when multiple drives are used. 2. Command to spin up is SET FEATURES (subcommand 07h). Refer to 12.28 Set Features. 3. To enable the CSEL mode (Cable Selection mode) the jumper block must be installed at E-F. In the CSEL mode the drive address is determined by AT interface signal #28 CSEL as follows: •...

  • Page 65: Environment

    7.2 Environment 7.2.1 Temperature and humidity Table 44: Temperature and humidity Operating conditions Temperature 5C to 55ºC (See note below) Relative humidity 8 to 90%, non-condensing Maximum wet bulb temperature 29.4ºC, non-condensing Maximum temperature gradient 15ºC/hour Altitude –300 to 3,048 m Non-operating conditions Temperature –40C to 65ºC...

  • Page 66: Corrosion Test

    7.2.2 Corrosion test The drive shows no sign of corrosion inside and outside of the hard disk assembly and is functional after being sub- jected to seven days at 50°C with 90% relative humidity. 7.3 DC power requirements Damage to the drive electronics may result if the power supple cable is connected or disconnected to the legacy power connector while power is being applied to the drive (no hot plug/unplug is alloweed).

  • Page 67: Table 48. Power Supply Current Of Sata Model

    Table 48: Power supply current of SATA model Power supply current of SATA +5 Volts [mA] +12 Volts [mA] Total model (values in milliamps. RMS) Pop Mean Std Dev Pop Mean Std Dev Idle average Idle ripple (peak-to-peak) Low RPM Idle Low RPM Idle Ripple Unload Idle average Unload Idle Ripple...

  • Page 68: Reliability

    7.4 Reliability 7.4.1 Data integrity No more than one sector is lost at Power loss condition during the write operation when the write cache option is disabled. If the write cache option is active, the data in write cache will be lost. To prevent the loss of customer data, it is recommended that the last write access before power off be issued after setting the write cache off.

  • Page 69: Mechanical Specifications

    7.5 Mechanical specifications 7.5.1 Physical dimensions and weight 2 5 .4 } 0 .4 1 0 1 .6 } 0 .4 1 4 6 } 0 .6 B R E A T H E R H O L E (*) D ia .

  • Page 70: Mounting Hole Locations

    7.5.2 Mounting hole locations The mounting hole locations and size of the drive are shown below. All dimensions are in mm. (6X) Max. penetration 4.5 mm Side View I/F Connector Bottom View (4X) Max. penetration 4.0 mm Figure 1: Mounting hole locations Thread 6-32 UNC 41.28±0.5...

  • Page 71: Connector Locations

    7.5.3 Connector locations SATA model 42.73 13.43 (3X) 33.39 5.08+/-0.1 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 72: Drive Mounting

    7.5.4 Drive mounting The drive will operate in all axes (6 directions). Performance and error rate will stay within specification limits if the drive is operated in the other orientations from which it was formatted. For reliable operation, the drive must be mounted in the system securely enough to prevent excessive motion or vibration of the drive during seek operation or spindle rotation, using appropriate screws or equivalent mounting hardware.

  • Page 73: Operating Vibration

    7.6 Vibration and shock All vibration and shock measurements recorded in this section are made with a drive that has no mounting attach- ments for the systems. The input power for the measurements is applied to the normal drive mounting points. 7.6.1 Operating vibration 7.6.1.1 Random vibration The test is 30 minutes of random vibration using the power spectral density (PSD) levels shown below in each of...

  • Page 74: Nonoperating Vibration

    7.6.2 Nonoperating vibration The drive does not sustain permanent damage or loss of previously recorded data after being subjected to the envi- ronment described below. 7.6.2.1 Random vibration The test consists of a random vibration applied in each of three mutually perpendicular axes for a duration of 10 minutes per axis.

  • Page 75: Table 55. Sound Power Levels

    7.6.4.2 Sinusoidal shock wave The shape is approximately half-sine pulse. The figure below shows the maximum acceleration level and duration. Table 54: Sinusoidal shock wave Acceleration level (G) Duration (ms) 7.6.5 Nonoperating rotational shock All shock inputs shall be applied around the actuator pivot axis. Table 55: Rotational shock Duration Rad/sec...

  • Page 76: Acoustics

    7.8 Identification labels The following labels are affixed to every drive: • A label containing the Hitachi logo, the Hitachi Global Storage Technologies part number and the statement " Made by Hitachi Global Storage Technologies Inc." or Hitachi Global Storage Technol- ogies approved equivalent.

  • Page 77: Safety

    United Nations Environment Program Montreal Protocol, and as ratified by the member nations. Material to be controlled include CFC-11, CFC-12, CFC-113, CFC-114, CFC-115, Halon 1211, Halon 1301 and Halon 2402. Although not specified by the Protocol, CFC-112 is also controlled. In addition to the Protocol Hitachi Global Stor- age Technologies requires the following: •...

  • Page 78: Electromagnetic Compatibility

    European Economic Community (EEC) directive number 76/889 related to the control of radio frequency interference and the Verband Deutscher Elektrotechniker (VDE) requirements of Austrailia. The SMA has approved two forms of C-Tick Marking for Hitachi Global Storage Technologies. 7.10.1 CE mark...

  • Page 79: General

    8.0 General 8.1 Introduction HDS7250xxKLAT80 This specification describes the host interface of . This is the main interface specification which includes the common host interface to both Parallel ATA and Serial ATA (SATA). The interface unique to ProductNameSATA Serial ATA model is described in the "Addendum for Serial ATA" of this specification. The interface conforms to the Working Document of Information technology - AT Attachment with Packet Interface Extension (ATA/ATAPI-7) Revision 4 dated on 23 December 2003 with certain limitations described in 2.0, "Deviations From Standard."...
  • Page 80 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 81: Registers

    9.0 Registers 9.1 Register set Table 58: Register Set Addresses Functions CS0- CS1- READ (DIOR-) WRITE (DIOW-) Data bus high impedance Not used Control block registers Data bus high impedance Not used Data bus high impedance Not used Alternate Status Device Control Device Address Not used...

  • Page 82: Alternate Status Register

    9.2 Alternate Status Register Table 59: Alternate Status Register DSC/ SERV This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt.

  • Page 83: Data Register

    9.6 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and the configuration information is transferred on an Identify Device command.

  • Page 84: Drive Address Register

    9.8 Drive Address Register Table 61: Drive Address Register -WTG -DS1 -DS0 This register contains the inverted drive select and head select addresses of the currently selected drive. Definitions High Impedance. This bit is not a device and will always be in a high impedance state. -WTG Write Gate.

  • Page 85: Error Register

    9.10 Error Register Table 63: Error Register IDNF ABRT TK0NF AMNF This register contains the status from the last command executed by the device or a diagnostic code. At the comple- tion of any command, except Execute Device Diagnostic, the contents of this register are always valid even if ERR = 0 is in the Status Register.

  • Page 86: Sector Number Register

    9.13 Sector Number Register This register contains the starting sector number for any disk data access for the subsequent command. The sector number is from one to the maximum number of sectors per track. In LBA mode, this register contains Bits 0–7. At the end of the command this register is updated to reflect the cur- rent LBA Bits 0–7.
  • Page 87 Index. IDX=1 once per revolution. Because IDX=1 only for a very short time during each revolu- tion, the host may not see it set to 1 even if the host is continuously reading the Status Register. Therefore the host should not attempt to use IDX for timing purposes. Error.
  • Page 88 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 89: General Operation

    10.0 General operation 10.1 Reset response ATA has the following three types of resets: The device executes a series of electrical circuitry diagnostics, spins up the Power On Reset (POR) head disk assembly, tests speed and other mechanical parametric, and sets default values.

  • Page 90: Register Initialization

    10.2 Register initialization After a power on, a hard reset, or a software reset, the register values are initialized as shown in the table below. Table 66: Default Register Values Register Default Value Error Diagnostic Code Sector Count Sector Number Cylinder Low Cylinder High Device/Head...

  • Page 91: Diagnostic And Reset Considerations

    10.3 Diagnostic and Reset considerations For each Reset and Execute Device Diagnostic, the diagnostic is done as follows: Power On Reset DASP– is read by Device 0 to determine if Device 1 is present. If Device 1 is present, Device 0 shall read PDIAG– to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error, otherwise Device 0 clears the BSY bit whenever it is ready to accept commands.

  • Page 92: Sector Addressing Mode

    10.4 Sector Addressing Mode All addressing of data sectors recorded on the device's media is done by a logical sector address. The logical CHS address for HDS7250xxKLAT80 is different from the actual physical CHS location of the data sector on the disk media.

  • Page 93: Power Management Features

    10.5 Power management features The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.

  • Page 94: Interface Capability For Power Modes

    10.5.4 Interface capability for power modes Each power mode affects the physical interface as defined in the following table: Table 69: Power conditions Mode Interface active Media Active Active Idle Active Standby Inactive Sleep Inactive Ready (RDY) is not a power condition. A device may post ready at the interface even though the media may not be accessible.

  • Page 95: Function

    10.6 S.M.A.R.T. Function The intent of Self-monitoring, analysis, and reporting technology (S.M.A.R.T.) is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, S.M.A.R.T. devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault condition.

  • Page 96: Error Log

    10.6.7 Error log Logging of reported errors is supported. The device provides information on the last five errors that the device reported as described in the SMART error log sector. The device may also provide additional vendor specific information on these reported errors. The error log is not disabled when SMART is disabled. Disabling SMART disables the delivering of error log information via the SMART READ LOG SECTOR command.

  • Page 97: Security Mode Feature Set

    10.7 Security Mode Feature Set Security Mode Feature Set is a powerful security feature. With a device lock password, a user can prevent unauthorized access to a device even if it is removed from the computer. New commands are supported for this feature as listed below: Security Set Password ('F1'h) Security Unlock...

  • Page 98: Passwords

    10.7.3 Passwords This function can have two types of passwords as described below. Master Password When the Master Password is set, the device does NOT enable the Device Lock Function, and the device CANNOT be locked with the Master Password, but the Master Password can be used for unlocking the locked device.
  • Page 99 10.7.4.3 Operation from POR after user password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed. Device Locked mode Unlock CMD Erase Prepare Media Access Non-media Access Command (*1) Command (*1) Erase Unit...
  • Page 100 10.7.4.4 User Password lost If the User Password is forgotten and High level security is set, the system user cannot access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.

  • Page 101: Command Table

    10.7.5 Command table This table shows the device's response to commands when the Security Mode Feature Set (Device lock function) is enabled. Table 70: Command table for device lock operation Device Mode Device Mode Command Command Locked Unlocked Frozen Locked Unlocked Frozen Check Power Mode...

  • Page 102: Host Protected Area Feature

    10.8 Host Protected Area Feature Host Protected Area Feature provides a protected area which cannot be accessed via conventional methods. This protected area is used to contain critical system data such as BIOS or system management information. The contents of the main memory of the entire system may also be dumped into the protected area to resume after a system power off.

  • Page 103: Security Extensions

    3. Conventional usage without system software support Since the drive works as a 6.2 GB device, there is no special care required for normal use of this device. 4. Advanced usage using protected area The data in the protected area is accessed by the following steps. i.

  • Page 104: Seek Overlap

    10.9 Seek overlap HDS7250xxKLAT80 provides an accurate method for measuring seek time. The seek command is usually used to measure the device seek time by accumulating the execution time for a number of seek commands. With typical implementation of seek command this measurement must include the device and host command overhead. To eliminate this overhead the drive overlaps the seek command as described below.

  • Page 105: Write Cache Function

    10.10 Write cache function Write cache is a performance enhancement whereby the device reports the completion of the write command (Write Sectors, Write Multiple, and Write DMA) to the host as soon as the device has received all of the data into its buffer. The device assumes the responsibility for subsequently writing the data onto the disk.

  • Page 106: Reassign Function

    10.11 Reassign function The Reassign function is used with read commands and write commands. The sectors of data for reassignment are prepared as the spare data sector. This reassignment information is registered internally and the information is available right after completing the Reassign function.

  • Page 107: Power-Up In Standby Feature Set

    10.12 Power-Up in Standby feature set The Power-Up In Standby feature set allows devices to be powered-up into the Standby power management state to minimize inrush current at power-up and to allow the host to sequence the spin-up of devices. This feature set will be enabled and disabled via the SET FEATURES command or the use of a jumper.

  • Page 108: Automatic Acoustic Management Feature Set (Aam)

    10.14 Automatic Acoustic Management feature set (AAM) This feature set allows the host to select an acoustic management level. The acoustic management level ranges the setting of 80h to FEh. Device performance and acoustic emanation may increase with increasing acoustic management levels.

  • Page 109: Address Offset Feature

    10.15 Address Offset Feature Computer systems perform initial code loading (booting) by reading from a predefined address on a disk drive. To allow an alternate bootable operating system to exist in a system reserved area on a disk drive this feature provides a Set Features function to temporarily offset the drive address space.

  • Page 110: Identify Device Data

    Table 72: Enable/Disable Address Offset Mode 10.15.2 Identify Device Data Identify Device data, word 83, bit 7 indicates the device supports the Address Offset Feature. Identify Device data, word 86, bit 7 indicates the device is in Address Offset mode. 10.15.3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error, even if the access protection is removed by a Set Max Address command.

  • Page 111: 48-Bit Address Feature Set

    10.16 48-bit Address Feature Set The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This allows device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that may be transferred by a single command are increased by increasing the allowable sector count to 16 bits. Commands unique to the 48-bit Address feature set are •...

  • Page 112: Streaming Commands

    • Write Stream PIO • Read Stream DMA • Write Stream DMA • Read Log Ext Support of the Streaming feature set is indicated in Identify Device word 84 bit 4. Note that PIO versions of these commands limit the transfer rate (16.6 MB/s), provide no CRC protection, and limit status reporting as compared to a DMA implementation.

  • Page 113: Read Continuous Bit

    10.17.5 Read Continuous bit If the Read Continuous bit is set to one for the command, the device shall transfer the requested amount of data to the host within the Command Completion Time Limit even if an error occurs. The data sent to the host by the device in an error condition is vendor specific.
  • Page 114 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 115: Command Protocol

    11.0 Command protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check to see if BSY = 1, and should proceed no further unless and until BSY = 0.

  • Page 116: Pio Data Out Commands

    e. The host reads one sector (or block) of data via the Data Register. f. The device sets DRQ = 0 after the sector (or block) has been transferred to the host. 4. For the Read Long command: a. The device sets BSY = 1 and prepares for data transfer. b.

  • Page 117: Non-Data Commands

    • Write Multiple • Write Multiple Ext • Write Sector(s) • Write Sector(s) Ext • Write Stream PIO Execution includes the transfer of one or more 512 byte (> 512 bytes on Write Long) sectors of data from the host to the device.
  • Page 118 • Device Configuration RESTORE • Execute Device Diagnostic • Flush Cache • Flush Cache Ext • Idle • Idle Immediate • Initialize Device Parameters • • Read Native Max ADDRESS • Read Native Max ADDRESS Ext • Read Verify Sector(s) •...

  • Page 119: Dma Commands

    11.4 DMA commands The following are DMA commands: • Read DMA • Read DMA Ext • Read Stream DMA • Write DMA • Write DMA • Write Stream DMA Data transfers using DMA commands differ in two ways from PIO transfers: •...
  • Page 120 Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...

  • Page 121: Command Descriptions

    12.0 Command descriptions The table below shows the commands that are supported by the device. Table 75: “Command Set (subcommand)” on page 109 shows the subcommands that are supported by each command or feature. Table 73: Command Set (1 of 2) Code Binary Code Bit Protocol...

  • Page 122: Table 73. Command Set (2 Of 2)

    Table 74: Command Set (2 of 2) Binary Code Bit Protocol Command Code (Hex) 7 6 5 4 3 2 1 0 Seek 0 1 1 1 - - - - Set Features 1 1 1 0 1 1 1 1 Set Max ADDRESS 1 1 1 1 1 0 0 1 Set Max ADDRESS Ext...

  • Page 123: Table 74. Command Set (Subcommand)

    4 : DMA command 5 : DMA queued command + : Vendor specific command Table 75: Command Set (subcommand) Command Feature Command (Subcommand) Code (Hex) Register (Hex) S.M.A.R.T. Function S.M.A.R.T. Read Attribute Values S.M.A.R.T. Read Attribute Thresholds S.M.A.R.T. Enable/Disable Attribute Autosave S.M.A.R.T.
  • Page 124 The following symbols are used in the command descriptions. Output registers This indicates that the bit must be set to 0. This indicates that the bit must be set to 1. The device number bit. Indicates that the device number bit of the Device/Head Register should be specified. Zero selects the master device and one selects the slave device.

  • Page 125: Check Power Mode (E5H/98H)

    12.1 Check Power Mode (E5h/98h) Table 76: Check Power Mode command (E5h/98h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 126: Configure Stream (51H)

    12.2 Configure Stream (51h) Table 77: Configure Stream Command (51h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 127 Feature Previous The default Command Completion Time Limit (CCTL). The value is calculated as follows: (Default CCTL) = ((content of the Features register)* (Identify Device words (99:98))) micriseconds. This time shall be used by the device when a streaming command with the same stream ID and a CCTL of zero is issued.

  • Page 128: Device Configuration Overlay (B1H)

    12.3 Device Configuration Overlay (B1h) Table 78: Check Power Mode Command (E5h/98h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 129: Device Configuration Identify (Subcommand C2H)

    12.3.3 DEVICE CONFIGURATION IDENTIFY (Subcommand C2h) The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure via PIO data-in transfer. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities, the response to an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command will reflect the reduced set of capabilities, while the DEVICE CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities.

  • Page 130: Table 79. Device Configuration Overlay Data Structure

    Table 80: Device Configuration Overlay Data structure Word Content 0001h Data Structure revision Multiword DMA modes supported 15-3 Reserved 1 = Multiword DMA mode 2 and below are supported 1 = Multiword DMA mode 1 and below are supported 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported 15-7 Reserved...

  • Page 131: Table 80. Dco Error Information Definition

    Table 81: DCO error information definition Cylinder high invalid word location Cylinder low invalid bit location (bits 15:8) Sector Number Invalid bit location (bits 7:0) Sector count error reason code description DCO feature is frozen Device is now Security Locked mode Device's feature is already modified with DCO User attempt to disable any feature enabled Device is now SET MAX Locked or Frozen mode...

  • Page 132: Download Microcode (92H)

    12.4 Download Microcode (92h) Table 82: Download Microcode Command (92h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 133: Execute Device Diagnostic (90H)

    12.5 Execute Device Diagnostic (90h) Table 83: Execute Device Diagnostic command (90h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 134: Flush Cache (E7H)

    12.6 Flush Cache (E7h) Table 84: Flush Cache command (E7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 135: Flush Cache Ext (Eah)

    12.7 Flush Cache Ext (EAh) Table 85: Flush Cache Ext Command (EAh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...

  • Page 136: Format Track (50H)

    12.8 Format Track (50h) Table 86: Format Track command (50h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 137: Format Unit (F7H)

    12.9 Format Unit (F7h) Table 87: Format Unit command (F7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 138: Identify Device (Ech)

    12.10 Identify Device (ECh) Table 88: Identify Device command (ECh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 139: Table 88. Identify Device Information (Part 1 Of 7)

    Table 89: Identify device information (Part 1 of 7) An asterisk (*) in next to the Content field indicates the use of those parameters that are vendor specific. Word Content Description 045AH or drive classi- bit assignments 045Eh fication 15(=0) 1=ATAPI device, 0=ATA device 14 - 8 retired...

  • Page 140: Table 89. Identify Device Information (Part 2 Of 7)

    Table 90: Identify device information (Part 2 of 7) An asterisk (*) in next to the Content field indicates the use of those parameters that are vendor specific Word Content Description 0000H Reserved XF00H Capabilities, bit assignments: 15-14(=0) Reserved Standby timer (=1) Values as specified in ATA standard are supported (=0)
  • Page 141 Table 91: Identify device information (Part 3 of 7) Word Content Description 0003H Flow Control PIO Transfer Modes Supported 15- 8(=0) Reserved 7- 0(=3) Advanced PIO Transfer Modes Supported '11' = PIO Mode 3 and 4 Supported 0078H Minimum Multiword DMA Transfer Cycle Time Per Word 15- 0(=78h) Cycle time in nanoseconds (120 ns, 16.6 MB/s) 0078H Manufacturer's Recommended Multiword DMA Transfer Cycle Time...
  • Page 142 Table 92: Identify device information (Part 4 of 7) Word Content Description 7FEBH Command set supported 15-14(=01) Word 83 is valid 13(=1) FLUSH CACHE EXT command supported 12(=1) FLUSH CACHE command supported 11(=1) Device Configuration Overlay command supported 10(=1) 48-bit Address Feature Set supported 9(=1) Automatic Acoustic mode 8(=1)
  • Page 143 XXXXH Command set/feature enabled Reserved NOP command READ BUFFER command WRITE BUFFER command Reserved Host Protected Area Feature Set DEVICE RESET command SERVICE interrupt RELEASE interrupt LOOK AHEAD WRITE CACHE PACKET Command Feature Set Power Management Feature Set Removable Feature Set Security Feature Set SMART Feature Set Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification...
  • Page 144 Table 93: Identify device information (Part 5 of 7 Word Content Description XXXXH Command set supported 15-14 Reserved FLUSH CACHE EXT command supported FLUSH CACHE command supported Device Configuration Overlay command supported 48-bit Address Feature Set supported Automatic Acoustic Management enabled SET Max Security extension enabled Set Features Address Offset Feature mode Set Features subcommand required to spin-up after...
  • Page 145 0x7FH Ultra DMA transfer modes 15- 8(=xx Current active Ultra DMA transfer mode Reserved (=0) Mode 6 1=Active 0=Not Active Mode 5 1=Active 0=Not Active Mode 4 1=Active 0=Not Active Mode 3 1=Active 0=Not Active Mode 2 1=Active 0=Not Active Mode 1 1=Active 0=Not Active...
  • Page 146 Table 94: Identify device information (Part 6 of 7) Word Content Description XXXXH Hardware reset result. Bit assignments 15-14 (=01) Word 93 is valid CBLID- status 1=above Vih 0=below Vil 12- 8 Device 1 hardware reset result Device 0 clear these bits to 0 Reserved PDIAG- assertion 1 = asset 0 = not assert...
  • Page 147 98-99 xxxxH Streaming Performance Granularity These words define the fixed unit of time that is used in Identify Device words (97:96) and (104),and Set Features subcommand 43h, and in the Streaming Performance Parameters log, which is accessed by use of the Read Log Ext command, and in the Command Completion Time Limit that is passed in streaming commands.
  • Page 148 Table 95: Identify device information (Part 7 of 7) An asterisk (*) in next to the Content field indicates the use of those parameters that are vendor specific Word Content Description xxxxH Current Set Feature Option. Bit assignments 15-4 Reserve Auto reassign 1= Enabled Reverting...

  • Page 149: Idle (E3H/97H)

    12.11 Idle (E3h/97h) Table 96: Idle command (E3h/97h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 150: Idle Immediate (E1H/95H)

    12.12 Idle Immediate (E1h/95h) Table 97: Idle Immediate command (E1h/95h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 151: Initialize Device Parameters (91H)

    12.13 Initialize Device Parameters (91h) Table 98: Initialize Device Parameters command (91h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 152: Read Buffer (E4H)

    12.14 Read Buffer (E4h) Table 99: Read Buffer (E4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 153: Read Dma (C8H/C9H)

    12.15 Read DMA (C8h/C9h) Table 100: Read DMA command (C8h/C9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 154 Sector Number This indicates the sector number of the last transferred sector. (L = 0). In LBA mode this register contains the current LBA bits 0–7. (L = 1) Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0). In LBA mode this register contains the current LBA bits 8–15 (Low) and bits16–23 (High).

  • Page 155: Read Dma Ext (25H)

    12.16 Read DMA Ext (25h) Table 101: Read DMA Ext Command (25h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 156 Cylinder High Current LBA (23:16) Cylinder High Previous LBA (47:40) Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24)of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8)of the address of the first unrecoverable error.

  • Page 157: Read Log Ext (2Fh)

    12.17 Read Log Ext (2Fh) Table 102: Read Log Ext Command (2Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 158 Table 103: Log Address Definition Log Address Content Feature set Type Log directory Read Only Extended Comprehensive SMART error log SMART error logging Ready Only SMART self-test log SMART self-test See Note Extended SMART self-test log SMART self-test Read Only Streaming Performance log Streaming Read Only...

  • Page 159: General Purpose Log Directory

    12.17.1 General Purpose Log Directory The figure below defines the 512 bytes that make up the General Purpose Log Directory. Table 104: General Purpose Log Directory Description Bytes Offset General purpose logging version Number of sectors in the log at log address 01h (7:0) Number of sectors in the log at log address 01h (15:8) Number of sectors in the log at log address 01h (7:0) Number of sectors in the log at log address 01h (15:8)

  • Page 160: Extended Comprehensive Smart Error Log

    12.17.2 Extended Comprehensive SMART Error Log The figure below defines the format of each of the sectors that comprise the Extended Comprehensive SMART error log. Error log data structure shall not include errors attributed to the receipt of faulty commands such as com- mand codes not implemented by the device or requests with invalid parameters or in valid addresses.
  • Page 161 12.17.2.3.2 Data format of command data structure Table 107: Command data structure Description Bytes Offset Device Control register Features register (7:0) (see Note) Features register (15:8) Sector count register(7:0) Sector count register(15:8) Sector number register(7:0) Sector number register(15:8) Cylinder Low register (7:0) Cylinder Low register (15:8) Cylinder High register (7:0) Cylinder High register (15:8)

  • Page 162: Extended Self-Test Log Sector

    Note: bits (7:0) refer to the contents if the register is read with bit 7 of the Device Control register cleared to zero. Bits (15:8) refer to the contents if the register is read with bit 7 of the Device Control register set to one. State shall contain a value indicating the state of the device when the command was issued to the device or the reset occurred as described below.

  • Page 163: Read Stream Error Log

    12.17.3.1 Self-test log data structure revision number The value of this revision number shall be 01h. 12.17.3.2 Self-test descriptor index This indicates the most recent self-test descriptor. If there have been no self-tests, this is set to zero. Valid values for the Self-test descriptor index are 0 to 18.

  • Page 164: Write Stream Error Log

    The Data Structure Version field shall contain a value of 02h indicating the second revision of the structure format. The Read Stream Error Log Count field shall contain the number of uncorrected sector entries currently reportable to the host. This value may exceed 31. The Error Log Index indicates the error log data structure representing the most recent error.

  • Page 165: Streaming Performance Log

    Error Log Index and Write Stream Error Count cleared to zero. The Write Stream Error Log is not reserved across power cycles and hardware reset. Table 112: Write Stream Error Log Description Bytes Offset Structure Version Error Log Index Write Stream Error Log Count Reserved Write Stream Error Log Entry #1 Write Stream Error Log Entry #2...
  • Page 166 Table 114: Sector Time Array Entry (Linearly Interpolated) Description Bytes LBA of reference location (LBA(7:0)...LBA(47:40)) (n+5) (Identify Device words (99:98))/65536 time units per (n+6) sector at the reference location (n+7) Table 115: Position Array Entry (Linearly Interpolated) Description Bytes LBA of start of region (LBA(7:0)...LBA(47:40)) (n+5) Position number in the range 0...32767 (n+6)

  • Page 167: Read Long (22H/23H)

    12.18 Read Long (22h/23h) Table 117: Read Long (22h/23h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 168 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred Sector Number This indicates the sector number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 0–7. (L = 1) Cylinder High/Low This indicates the cylinder number of the transferred sector.

  • Page 169: Read Multiple (C4H)

    12.19 Read Multiple (C4h) Table 118: Read Multiple (C4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 170 Cylinder High/Low This indicates the cylinder number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 8–15 (Low), 16–23 (High). (L = 1) This indicates the head number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 24–27.

  • Page 171: Read Multiple Ext (29H)

    12.20 Read Multiple Ext (29h) Table 119: Read DMA Ext Command (25h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 172 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.

  • Page 173: Read Native Max Address (F8H)

    12.21 Read Native Max ADDRESS (F8h) Table 120: Read Native Max ADDRESS (F8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...

  • Page 174: Read Native Max Address Ext (27H)

    12.22 Read Native Max Address Ext (27h) Table 121: Read Native Max Address Ext command (27h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...

  • Page 175: Read Sectors (20H/21H)

    12.23 Read Sectors (20h/21h) Table 122: Read Sectors Command (20h/21h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 176 Cylinder High/Low This is the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This is the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.

  • Page 177: Read Sector(S) Ext (24H)

    12.24 Read Sector(s) Ext (24h) Table 123: Read Sector(s) Ext command (24h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 178 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.

  • Page 179: Read Stream Dma (2Ah)

    12.25 Read Stream DMA (2Ah) Table 124: Read Stream DMA Command (2Ah) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 180 Feature Current URG (bit7) URG specifies an urgent transfer request. The Urgent bit specifies that the com- mand should be completed in the minimum possible time by the device and shall be completed within the specified Command Completion Time Limit. RC (bit6) RC specifies Read Continuous mode enabled.
  • Page 181 Cylinder High Previous LBA (47:40). Input Parameters From The Device Sector Number LBA (7:0) of the address of the first unrecoverable error. (HOB=0) Sector Number LBA (31:24) of the address of the first unrecoverable error. (HOB=1) Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.

  • Page 182: Read Stream Pio (2Bh)

    12.26 Read Stream PIO (2Bh) Read Stream PIO Command (2Bh) Table 125: Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 183 Output Parameters From The Device Feature Current URG (bit7) URG specifies an urgent transfer request. The Urgent bit specifies that the command should be completed in the minimum possible time by the device and shall be completed within the specified Command Completion Time Limit. RC (bit6) RC specifies Read Continuous mode enabled.
  • Page 184 Sector Number LBA (7:0) of the address of the first unrecoverable error. (HOB=0) Sector Number LBA (31:24) of the address of the first unrecoverable error. (HOB=1) Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error. Cylinder High LBA (23:16) of the address of the first unrecoverable error.

  • Page 185: Read Verify Sectors (40H/41H)

    12.27 Read Verify Sectors (40h/41h) Table 126: Read Verify Sectors (40h/41h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 186 Cylinder High/Low This is the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This is the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.

  • Page 187: Read Verify Sector(S) (42H)

    12.28 Read Verify Sector(s) (42h) Table 127: Read Verify Sector(s) command (42h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 188 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.

  • Page 189: Recalibrate (1Xh)

    12.29 Recalibrate (1xh) Table 128: Recalibrate (1xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 190: Security Disable Password (F6H)

    12.30 Security Disable Password (F6h) Table 129: Security Disable Password (F6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 191: Security Disable Password (F3H)

    12.31 Security Disable Password (F3h) Table 131: Security Disable Password (F3h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 192: Security Erase Unit (F4H)

    12.32 Security Erase Unit (F4h) Table 132: Security Erase Unit (F4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 193 If the device receives a Security Erase Unit command without a prior Security Erase Prepare command the device aborts the security erase unit command. This command disables the security mode feature (device lock function), however, the master password is still stored internally within the device and may be reactivated later when a new user password is set.

  • Page 194: Security Freeze Lock (F5H)

    12.33 Security Freeze Lock (F5h) Table 134: Security Freeze Lock command (F5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 195: Security Set Password (F1H)

    12.34 Security Set Password (F1h) Table 135: Security Set Password command (F1h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 196 Security Level Zero indicates High level. One indicates Maximum level. If the host sets High level and the password is forgotten, the Master Password can be used to unlock the device. If the host sets Maximum level and the user password is for- gotten, only a Security Erase Prepare/Security Unit command can unlock the device and all data will be lost.

  • Page 197: Security Unlock (F2H)

    12.35 Security Unlock (F2h) Table 137: Security Unlock command (F2h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 198: Seek (7Xh)

    12.36 Seek (7xh) Table 138: Seek command (7xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 199: Set Features (Efh)

    12.37 Set Features (EFh) Table 139: Set Features command (EFh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 200: Set Transfer Mode

    Disable release interrupt Note: After the power on reset or hard reset the device is set to the following features as default. Write cache Enable ECC bytes 4 bytes Read look-ahead Enable Reverting to power on defaults Disable Release interrupt Disable 12.37.1 Set Transfer mode When the Feature register is 03h (= Set Transfer mode) the Sector Count Register specifies the transfer mechanism.

  • Page 201: Automatic Acoustic Management

    When Low RPM standby mode is the deepest Power Saving mode and the value in Sector Count register is between 40h and 7Fh, 120 ☯y ☯435 [sec] (default: 120 [sec]) = (x − 40h) 60 +600 (600 ☯y ☯4380) [sec] When Low RPM standby mode is the deepest Power Saving Mode and the value in Sector Count register is between 01h and 3Fh, where...

  • Page 202: Set Maximum Host Interface Sector Time

    12.37.5 Set Maximum Host Interface Sector Time Sector Count Typical PIO Mode Host Interface Sector Time (7:0) LBA Low Typical PIO Mode Host Interface Sector Time (15:8) LBA Mid Typical DMA Mode Host Interface Sector Time (7:0) LBA High Typical DMA Mode Host Interface Sector Time (15:8) Subcommand code 43h allows the host to inform the device of a host interface rate limitation.

  • Page 203: Set Max Address (F9H)

    12.38 Set Max ADDRESS (F9h) Table 140: Set Max ADDRESS command (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 204 If a host protected area has been established by a Set Max Address Ext command, the device shall return command aborted. Output parameters to the device Option bit for selection whether nonvolatile or volatile. B = 0 is volatile condition. When B=1, MAX LBA/CYL which is set by Set Max LBA/CYL command is preserved by POR.

  • Page 205: Set Max Set Password (Feature=01H)

    12.38.1 Set Max Set Password (Feature=01h) Table 141: Set Max Set Password command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...

  • Page 206: Set Max Lock (Feature=02H)

    12.38.2 Set Max Lock (Feature=02h) Table 143: Set Max Lock command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 207: Set Max Unlock (Feature = 03H)

    12.38.3 Set Max Unlock (Feature = 03h) Table 144: Set Max Unlock command (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data...

  • Page 208: Set Max Freeze Lock (Feature = 04H)

    12.38.4 Set Max Freeze Lock (Feature = 04h) Table 145: Set Max Freeze Lock (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data...

  • Page 209: Set Max Address Ext (37H)

    12.39 Set Max Address Ext (37h) Table 146: Set Max Address Ext command (37h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
  • Page 210 Output parameters to the device Option bit for selection whether nonvolatile or volatile. B=0 is volatile condition. When B=1, MAX Address which is set by the Set Max Address Ext command is preserved by POR. When B=0, MAX Address which is set by the Set Max Address Ext command will be lost by POR.

  • Page 211: Set Multiple (C6H)

    12.40 Set Multiple (C6h) Table 147: Set Multiple command (C6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 212: Sleep (E6H/99H)

    12.41 Sleep (E6h/99h) Table 148: Sleep command (E6h/99h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 213: Function Set (B0H)

    12.42 S.M.A.R.T. Function Set (B0h) Table 149: S.M.A.R.T. Function Set command (B0h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 214 12.42.1.2 S.M.A.R.T. Read Attribute Thresholds (subcommand D1h) This subcommand returns the Attribute Thresholds of the device to the host. Upon receipt of the SMART Read Attribute Thresholds subcommand from the host, the device reads the Attribute Thresholds from the Attribute Threshold sectors and then transfers the 512 bytes of Attribute Thresholds information to the host.
  • Page 215 Off-line mode: The device executes command completion before executing the specified routine. During execu- tion of the routine the device will not set BSY nor clear DRDY. If the device is in the process of performing its rou- tine and is interrupted by a new command from the host, the device will abort or suspend its routine and service the host within two seconds after receipt of the new command.
  • Page 216 12.42.1.9 S.M.A.R.T. Disable Operations (subcommand D9h) This subcommand disables all S.M.A.R.T. capabilities within the device including the attribute Autosave feature of the device. After receipt of this subcommand the device disables all S.M.A.R.T. operations. Non self-preserved Attribute Values will no longer be monitored. The state of S.M.A.R.T.—either enabled or disabled—is preserved by the device across power cycles.

  • Page 217: Device Attribute Data Structure

    12.42.2 Device Attribute Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values subcommand. All multibyte fields shown in these data structures are in byte ordering, that is, the least significant byte occupies the lowest numbered byte address location in the field.
  • Page 218 Attribute ID Numbers: Any nonzero value in the Attribute ID Number indicates an active attribute. The device supports following Attribute ID Numbers. Attribute Name Indicates that this entry in the data structure is not used Raw Read Error Rate Throughput Performance Spin Up Time Start/Stop Count Reallocated Sector Count...
  • Page 219 12.42.2.3 Off-Line Data Collection Status The value of this byte defines the current status of the off-line activities of the device. Bit 7 indicates an Automatic Off-line Data Collection Status. Bit 7 Automatic Off-line Data Collection Status Automatic Off-line Data Collection is disabled. Automatic Off-line Data Collection is enabled.

  • Page 220: Device Attribute Thresholds Data Structure

    Abort/restart off-line by host bit The device will suspend off-line data collection activity after an interrupting command and resume it after a vendor specific event The device will abort off-line data collection activity upon receipt of a new command Off-line Read Scanning implemented bit The device does not support Off-line Read Scanning The device supports Off-line Read Scanning Self-test implemented bit...
  • Page 221 these data structures are in byte ordering, that is, that the least significant byte occupies the lowest numbered byte address location in the field. The sequence of active Attribute Thresholds will appear in the same order as their corresponding Attribute Values. Table 152: Device Attribute Thresholds Data Structure Description Byte...

  • Page 222: Log Directory

    12.42.4 S.M.A.R.T. Log Directory The following table defines the 512 bytes that make up the S.M.A.R.T. Log Directory. The S.M.A.R.T. Log Direc- tory is S.M.A.R.T. Log Address zero and is defined as one sector long. Table 154: S.M.A.R.T. Log Directory Description Byte Offset...
  • Page 223 12.42.5.4 Error log data structure The data format of each error log data structure is shown below. Table 156: Error log data structure Description Byte Offset 1st command data structure 2nd command data structure 3rd command data structure 4th command data structure 5th command data structure Error data structure 12.42.5.5 Command data structure...

  • Page 224: Self-Test Log Data Structure

    The state field contains a value indicating the device state when command was issued to the device. Value State Unknown Sleep Standby Active/Idle S.M.A.R.T. Off-line or Self-test x5h-xAh Reserved xBh-xFh Vendor specific The value of ’x’ is vendor specific 12.42.6 Self-test log data structure The following table defines the 512 bytes that make up the Self-test log sector.

  • Page 225: Selective Self-Test Log Data Structure

    12.42.7 Selective self-test log data structure The Selective self-test log is a log that may be both written and read by the host. This log allows the host to select the parameters for the self-test and to monitor the progress of the self-test. The following table defines the contents of the Selective self-test log which is 512 bytes long.

  • Page 226: Error Reporting

    12.42.8 Error reporting The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device. Table 161: S.M.A.R.T. Error Codes Error condition Status Register Error Register A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being loaded into the Cylinder High and Cylin- der Low registers.

  • Page 227: Standby (E2H/96H)

    12.43 Standby (E2h/96h) Table 162: Standby (E2h/96h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 228: Standby Immediate (E0H/94H)

    12.44 Standby Immediate (E0h/94h) Table 163: Standby Immediate (E0h/94h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 229: Write Buffer (E8H)

    12.45 Write Buffer (E8h) Table 164: Write Buffer (E8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 230: Write Dma (Cah/Cbh)

    12.46 Write DMA (CAh/CBh) Table 165: Write DMA (CAh/CBh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 231 Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.

  • Page 232: Write Dma Ext (35H)

    12.47 Write DMA Ext (35h) Table 166: Write DMA Ext Command (35h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 233 Cylinder High Current LBA (23:16) Cylinder High Previous LBA (47:40) Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error.

  • Page 234: Write Log Ext (3Fh)

    12.48 Write Log Ext (3Fh) Table 167: Write Log Ext Command (3Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...

  • Page 235: Write Long (32H/33H)

    12.49 Write Long (32h/33h) Table 168: Write Long (32h/33h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 236 Cylinder High/Low This indicates the cylinder number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This indicates the head number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 24–27.

  • Page 237: Write Multiple (C5H)

    12.50 Write Multiple (C5h) Table 169: Write Multiple (C5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 238 Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains current the LBA bits 24–27.

  • Page 239: Write Multiple Ext (39H)

    12.51 Write Multiple Ext (39h) Table 170: Write Log Ext Command (3Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 240 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.

  • Page 241: Write Sectors (30H/31H)

    12.52 Write Sectors (30h/31h) Table 171: Write Sectors command (30h/31h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 242 Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.

  • Page 243: Write Sector(S) Ext (34H)

    12.53 Write Sector(s) Ext (34h) Table 172: Write Sector(s) Command (34h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 244 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.

  • Page 245: Write Stream Dma (3Ah)

    12.54 Write Stream DMA (3Ah) Table 173: Write Stream DMA Command (3Ah) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 246 WC (bit6) WC specifies Write Continuous mode enabled. If the Write Continuous bit is set to one, the device shall not stop execution of the command due to errors. If the WC bit is set to one and errors occur in transfer or writing of the data, the device shall continue to transfer the amount of data requested and then provide ending status with BSY bit cleared to zero, the SE bit set to one, the ERR bit cleared to zero, and the type of error, ICRC, IDNF or ABRT reported in the error...
  • Page 247 SE (Status, bit 5) SE (Stream Error) shall be set to one if an error has occurred during the execution of the command and the WC bit is set to one, In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error, and the Sector Count registers shall contain the number of consecutive sectors that may contain errors.

  • Page 248: Write Stream Pio (3Bh)

    12.55 Write Stream PIO (3Bh) Table 174: Write Stream PIO Command (3Bh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
  • Page 249 (bit6) WC specifies Write Continuous mode enabled. If the Write Continuous bit is set to one, the device shall not stop ex- ecution of the command due to errors. If the WC bit is set to one and errors occur in transfer or writing of the data, the device shall continue to transfer the amount of data requested and then provide ending status with BSY bit cleared to zero, the SE bit set to one, the ERR...
  • Page 250 Cylinder High LBA (47:40). Previous Input Parameters From The Device Sector Number LBA (7:0) of the address of the first unrecoverable error. (HOB=0) Sector Number LBA (31:24) of the address of the first unrecoverable error. (HOB=1) Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.

  • Page 251: Time-Out Values

    13.0 Time-out values The timing of BSY and DRQ in Status Register are shown in the table below. Table 175: Time-out values INTERVAL START STOP TIME-OUT Power On Device Busy After Power Power On Status Register BSY=1 400 ns Device Ready After Power On Status Register BSY=1 31 sec...
  • Page 252 Index 48-bit Address Feature ....................97 Abbreviations ........................1 Acoustics .........................61 Actuator ..........................9 actuator lock ........................57 Address Offset ........................95 Advanced Power Managemen ..................93 Advanced Power Management feature set (APM) ............93 Alternate Status Register ....................68 AT signal connector ......................24 Attribute thresholds ......................81 Attribute values .......................81 Attributes ........................81 Auto Reassign .........................92 Automatic Acoustic Management ..................94...
  • Page 253 Cylinder allocation ......................12, 13 Cylinder High Register ....................68 Data In commands ......................101 Data Out Commands .......................102 Data Register ........................69 Data Reliability .......................53 Data sheet ........................11, 12 Data transfer speed ......................17 DC power requirements ....................51 Defect flagging strategy ....................21 Deviations from standard ....................65 Device Pausing Write DMA ...................40 Device/Head Register .....................70 Diagnostic and Reset considerations ................77...
  • Page 254 Format Unit (F7h) ......................123 Formatted capacity ......................11 Functional specification ....................7 General ..........................1 General features ......................5 General operation ......................75 German safety mark ......................62 Head disk assembly ......................9 Head disk assembly data ....................9 Heads unload ........................57 Host Terminating Write DMA ..................42 Humidity .........................50 Identification labels ......................61 Identify Device (ECh) .....................124 Idle (E3h/97h) .........................135...
  • Page 255 Load/unload ........................53 Logical CHS addressing mode ..................78 Mechanical positioning ....................15 Mechanical specifications ....................54 Mode transition time .......................19 Mounting hole locations ....................54, 55 Mounting orientation ......................57 Non-data commands .......................103 Off-line read scanning ....................81 Operating modes ......................19 description 17 Operating shock ......................59 Operating vibration ......................58 Operation example ......................84 Packaging ........................63...
  • Page 256 Read DMA (C8h/C9h) ....................139 Read DMA Ext (25h) ......................141 Read Log Ext (2Fh) ......................143 Read Long (22h/23h) ......................153 Read Stream DMA (2Ah) ....................165 Read Verify Sector(s) (42h) ....................173 Reassign function ......................92 References ........................1 Register set ........................67 Registers ..........................67 Reliability ........................53 Reset response .........................75 Reset timings ........................31 S.M.A.R.T.
  • Page 257 Signal descriptions ......................26 Signal timings .........................31 Sleep (E6h/99h) ......................198 Specification ........................23, 45 Standby (E2h/96h) ......................213 Standby Immediate ......................214 Standby timer ........................79 Start/stop cycles ......................53 Status Register ........................72 Streaming commands ......................98 Streaming feature Set ......................97 Streaming Logs .......................99 Streaming Performance log ....................151 Temperature ........................50 Terminology ........................65 Threshold exceeded condition ..................81...
  • Page 258 References in this publication to Hitachi Global Storage Technologies products, programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates. Product information is provided for information pur- poses only and does not constitute a warranty.

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