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Address Register
Data Bus
(low)
Name
Width
H'A0
TPMR
8
H'A1
TPCR
8
H'A2
NDERB
8
H'A3
NDERA
8
1
H'A4
NDRB*
8
8
1
H'A5
NDRA*
8
8
1
H'A6
NDRB*
8
8
1
H'A7
NDRA*
8
8
2
H'A8
TCSR*
8
2
H'A9
TCNT*
8
H'AA
—
2
H'AB
RSTCSR*
8
H'AC
—
H'AD
—
H'AE
—
H'AF
—
H'B0
SMR
8
H'B1
BRR
8
H'B2
SCR
8
H'B3
TDR
8
H'B4
SSR
8
H'B5
RDR
8
H'B6
SCMR
8
H'B7
Notes: 1. The address depends on the output trigger setting.
2. For write access to TCSR, TCNT, and RSTCSR, see section 10.2.4, Notes on Register
Access.
Legend
TPC:
Programmable timing pattern controller
WDT: Watchdog timer
SCI:
Serial communication interface
Bit 7
Bit 6
Bit 5
—
—
—
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
NDER7
NDER6 NDER5
NDR15
NDR14
NDR13
NDR15
NDR14
NDR13
NDR7
NDR6
NDR5
NDR7
NDR6
NDR5
—
—
—
—
—
—
—
—
—
—
—
—
OVF
WT/IT
TME
—
—
—
WRST
RSTOE —
—
—
—
—
—
—
—
—
—
—
—
—
C/A
CHR
PE
TIE
RIE
TE
TDRE
RDRF
ORER
—
—
—
Bit Names
Bit 4
Bit 3
Bit 2
—
G3NOV
G2NOV G1NOV
NDER4 NDER3
NDER2 NDER1
NDR12
NDR11
NDR10
NDR12
—
—
NDR4
NDR3
NDR2
NDR4
—
—
—
—
—
—
NDR11
NDR10
—
—
—
—
NDR3
NDR2
—
—
CKS2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O/E
STOP
MP
RE
MPIE
TEIE
FER
PER
TEND
—
SDIR
SINV
Bit 1
Bit 0
Module Name
G0NOV TPC
NDER8
NDER0
NDR9
NDR8
—
—
NDR1
NDR0
—
—
—
—
NDR9
NDR8
—
—
NDR1
NDR0
CKS1
CKS0
WDT
—
—
—
—
—
—
—
—
—
—
—
—
CKS1
CKS0
SCI0
CKE1
CKE0
MPB
MPBT
—
SMIF
Smart card
interface
573
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