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Table 15.3 Control Signal Timing (cont)
V
= 1.8 V to 5.5 V, AV
CC
(including subactive mode) unless otherwise indicated.
Item
Symbol Pins
Input pin high width t
IH
Input pin low width
t
IL
UD pin minimum
t
UDH
modulation width
t
UDL
Notes: 1. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
2. Internal power supply step-down circuit not used
3. Figures in parentheses are the maximum t
Table 15.4 Serial Interface (SCI3-1, SCI3-2) Timing
V
= 1.8 V to 5.5 V, AV
CC
(including subactive mode) unless otherwise indicated.
Item
Input clock
Asynchronous
cycle
Synchronous
Input clock pulse width
Transmit data delay time
(synchronous)
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
Note:
1. When internal step-down circuit is not used.
= 1.8 V to 5.5 V, V
CC
Applicable
Min
IRQ
to IRQ
,
2
0
4
WKP
to WKP
0
7
ADTRG, TMIC
TMIF, TMIG,
AEVL, AEVH
IRQ
to IRQ
,
2
0
4
WKP
to WKP
,
0
7
ADTRG, TMIC,
TMIF, TMIG,
AEVL, AEVH
UD
4
= 1.8 V to 5.5 V, V
CC
Values
Symbol Min
Typ
t
4
—
scyc
6
—
t
0.4
—
SCKW
t
—
—
TXD
—
—
t
200.0
—
RXS
400.0
—
t
200.0
—
RXH
400.0
—
= AV
= 0.0 V, T
SS
SS
Values
Typ
Max
Unit
—
—
t
cyc
t
subcyc
—
—
t
cyc
t
subcyc
—
—
t
cyc
t
subcyc
rate with external clock input.
OSC
= AV
= 0.0 V, T
SS
SS
Max
Unit
Test Conditions
—
t
or
cyc
—
t
subcyc
0.6
t
scyc
1
t
or
V
cyc
CC
1
t
Except the above
subcyc
—
ns
V
CC
—
Except the above
—
ns
V
CC
—
Except the above
= –20°C to +75°C
a
Reference
Test Condition
Figure
Figure 15.3
Figure 15.3
Figure 15.4
= –20°C to +75°C
a
Reference
Figure
Figure 15.5
Figure 15.5
= 4.0 V to 5.5 V Figure 15.6
= 4.0 V to 5.5 V Figure 15.6
Figure 15.6
= 4.0 V to 5.5 V Figure 15.6
Figure 15.6
*1
*1
367
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