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IRR1—Interrupt request register 1
Bit
7
IRRTA
Initial value
0
Read/Write
R/(W)*
Timer A interrupt request flag
0 Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
1 Setting conditions:
When the timer A counter value overflows (rom H'FF to H'00)
Note: * Bits 7 and 4 to 0 can only be written with 0, for flag clearing.
6
5
—
—
IRRI4
0
1
R/W
—
R/(W)*
IRQ4 to IRQ0 interrupt request flags
0 Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQn is designated for interrupt
input and the designated signal edge is input
H'F6
4
3
2
IRRI3
IRRI2
0
0
0
R/(W)*
R/(W)*
System control
1
0
IRRI1
IRRI0
0
0
R/(W)*
R/(W)*
(n = 4 to 0)
443
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