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Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as
follows.
Bit 1
Bit 0
DIV1
DIV0
Frequency Division Ratio
0
0
1/1
0
1
1/2
1
0
1/4
1
1
1/8
18.5.3
Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time t
operating frequency range, and ensure that ø does not fall below this lower limit.
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in the
division ratio. The waiting time for exit from software standby mode also changes when the
division ratio is changed. For details, see section 19.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
556
in the AC electrical characteristics. Set ømin to the lower limit of the
cyc
(Initial value)
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