9.0 Registers
Addresses
CS0–
CS1–
DA2
DA1
N
N
x
N
A
0
N
A
1
N
A
1
N
A
1
A
N
0
A
N
0
A
N
0
A
N
0
A
N
0
A
N
1
A
N
1
A
N
1
A
N
1
A
N
1
A
N
1
A
N
1
A
A
x
1
Mapping of registers in LBA mode
Logic conventions:
Figure 66. Register Set
Communication to or from the device is through an I/ O Register that routes the input or output data to or
from registers addressed by the signals from the host (CS0 – , CS1 – , DA2, DA1, DA0, DIOR – and
DIOW – ).
The Command Block Registers are used for sending commands to the device or posting status from the
device.
The Control Block Registers are used for device control and to post alternate status.
DA0
READ (DIOR–)
x
x
Data bus high impedance
x
x
Data bus high impedance
0
x
Data bus high impedance
1
0
Alternate Status
1
1
Device Address
0
0
Data
0
1
Error Register
1
0
Sector Count
1
1
Sector Number
1
1
LBA bits 0–7
0
0
Cylinder Low
0
0
LBA bits 8–15
0
1
Cylinder High
0
1
LBA bits 16–23
1
0
Device/Head.
1
0
LBA bits 24–27
1
1
Status
x
x
A = signal asserted
N = signal negated
X = may be A or N
Deskstar 40GV & 75GXP hard disk drive specifications
Functions
Not used
Control block registers
Not used
Not used
Device Control
Not used
Command block registers
Data
Features
Sector Count
Sector Number
1
2 LBA bits 0–7
Cylinder Low
1
2 LBA bits 8–15
Cylinder High
1
2 LBA bits 16–23
Device/Head
1
2 LBA bits 24–27
Command
Invalid address
69
WRITE (DIOW–)
1
1
1
1