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IBM IC35L020 - Deskstar 20 GB Hard Drive Specifications
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IBM IC35L020 - Deskstar 20 GB Hard Drive Specifications

IBM IC35L020 - Deskstar 20 GB Hard Drive Specifications

Hard drive specifications
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IBM storage products—official published specification

Hard disk drive specifications

Deskstar 60GXP
3.5 inch Ultra ATA/100 hard disk drive
Models:
IC35L010AVER07
IC35L020AVER07
IC35L030AVER07
IC35L040AVER07
IC35L060AVER07
Revision 2.2
S07N-4780-04
1 May 2002
Publication #2818

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Summary of Contents for IBM IC35L020 - Deskstar 20 GB Hard Drive

  • Page 1: Hard Disk Drive Specifications

    IBM storage products—official published specification Hard disk drive specifications Deskstar 60GXP 3.5 inch Ultra ATA/100 hard disk drive Models: IC35L010AVER07 IC35L020AVER07 IC35L030AVER07 IC35L040AVER07 IC35L060AVER07 Revision 2.2 1 May 2002 S07N-4780-04 Publication #2818...
  • Page 2 IBM storage products—official published specification...
  • Page 3 IBM storage products—official published specification Hard disk drive specifications Deskstar 60GXP 3.5 inch Ultra ATA/100 hard disk drive Models: IC35L010AVER07 IC35L020AVER07 IC35L030AVER07 IC35L040AVER07 IC35L060AVER07 Revision 2.2 1 May 2002 S07N-4780-04 Publication #2818...
  • Page 4 IBM may have patents or pending patent applications covering subject matter in this document. The furnishing of this document does not give you any license to these patents. You can send license inquiries in writing to the IBM Director of Commercial Relations, IBM Corporation, Armonk, NY 10577.

  • Page 5: Table Of Contents

    Table of contents ..............List of Figures .
  • Page 6 ..........9.2.1 Temperature and humidity .
  • Page 7 ............12.7 Drive Address Register .
  • Page 8 ............14.2 PIO Data Out commands .
  • Page 9 ......15.32.10 S.M.A.R.T. Return Status (Subcommand DAh) ....15.32.11 S.M.A.R.T.
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  • Page 11: List Of Figures

    List of Figures ............Figure 1.
  • Page 12 Figure 48. Typical current wave form of the 12 V line at drive start up—listed by drive model ............. . . capacity .
  • Page 13 ......... . . Figure 93.
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  • Page 15: General

    1.0 General This document describes the specifications of the following IBM 3.5-inch ATA interface hard disk drives: IC35L010AVER07 (10 GB) IC35L020AVER07 (20 GB) IC35L030AVER07 (30 GB) IC35L040AVER07 (40 GB) IC35L060AVER07 (60 GB) The specifications in this document are subject to change without notice.
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  • Page 17: General Features

    2.0 General features Data capacities of 20 GB, 40 GB, and 60 GB Enhanced IDE (ATA-5) interface Sector format of 512 bytes/sector Closed Loop actuator servo A Load/Un-load mechanism with no head-to-disk contact during start/stop Automatic actuator lock Interleave factor 1:1 Seek time of 8.5 ms in Read Operation (8.2 ms typical without Command Overhead) Size of sector buffer is 2048 KB Upper 132 KB used for firmware...
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  • Page 19: Part 1. Functional Specification

    Part 1. Functional specification Deskstar 60 GXP Hard disk drive specification...
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  • Page 21: Fixed Disk Subsystem Description

    3.0 Fixed disk subsystem description 3.1 Control Electronics The drive is electronically controlled by a microprocessor, several logic modules, digital/analog modules, and various drivers and receivers. The control electronics performs the following major functions: Controls and interprets all interface signals between the host controller and the drive Controls read write accessing of the disk media, including defect management and error recovery Controls starting, stopping, and monitoring of the spindle Conducts a power-up sequence and calibrates the servo...
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  • Page 23: Fixed Disk Characteristics

    4.0 Fixed disk characteristics 4.1 Formatted capacity Drive capacity 10 GB 20 GB 30 GB 40 GB 60 GB Physical Layout Label capacity (GB) 20.5 30.7 61.5 Bytes per sector Sectors per track 373–780 373–780 373–780 373–780 373–780 Number of data heads Number of data disks Data sectors per 373–780...

  • Page 24: Performance Characteristics

    4.3 Performance Characteristics A file performance is characterized by the following parameters: Command Overhead Mechanical Positioning • Seek Time • Latency Data Transfer Speed Buffering Operation (Look ahead/Write cache) Note: All the above parameters contribute to file performance. There are other parameters that contribute to the performance of the actual system.

  • Page 25: Figure 5. Full Stroke Seek Time

    The terms "Typical" and "Max" are used throughout this specification with the following meanings: Typical. The average of the drive population tested at nominal environmental and voltage conditions. Maximum or Max. The maximum value measured on any one drive over the full range of the environmental and voltage conditions.

  • Page 26: Drive Ready Time

    A cylinder switch time is defined as the amount of time required by the fixed disk to complete seek the next sequential block after reading the last track in the current cylinder. The measurement method is given in section 4.3.6, "Throughput" on page 13. 4.3.2.5 Single Track Seek Time (Without Command Overhead, Including Settling) Function Typical...

  • Page 27: Data Transfer Speed-60 Gb Model

    4.3.4 Data Transfer Speed—60 GB model Description Mb/s Disk-Buffer Transfer (Zone 0) Instantaneous (Typical) 48.0 Sustained (read Typical) 40.8 Disk-Buffer Transfer (Zone 17) Instantaneous (Typical) 24.6 Sustained (read Typical) 19.5 Buffer-Host (maximum) Figure 11. Data Transfer Speed Instantaneous Disk-Buffer Transfer Rate (Mbyte/sec) is derived by: (Number of Sectors on a track) * 512 * (Revolution/sec) Note: Number of sectors per track will vary because of the linear density recording.

  • Page 28: Figure 13. Random Access Performance

    T = A + B + C + (16,777,216/D) + (512/E) (READ) where T = Calculated time (in seconds) A = Command process time (Command Overhead) (in seconds) B = Average seek time (in seconds) C = Average latency (in seconds) D = Sustained disk-buffer transfer rate (bytes/s) E = Buffer-host transfer rate (bytes/s) 4.3.6.2 Random access...

  • Page 29: Operating Modes

    4.3.7 Operating modes Operating mode Description Spin-up Start up time period from spindle stop or power down Seek Seek operation mode Write Write operation mode Read Read operation mode Low RPM Idle Spindle rotation @4,500 RPM with heads unloaded Unload Idle Spindle rotation @7,200 RPM with heads unloaded The spindle motor and servo system are working Idle...
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  • Page 31: Defect Flagging Strategy

    5.0 Defect flagging strategy Media defects are remapped to the next available sector during the Format Process in manufacturing. The mapping from LBA to the physical locations is calculated by an internally maintained table. Shipped format Data areas are optimally used. No extra sector is wasted as a spare throughout user data areas.
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  • Page 33: Data Integrity

    6.0 Data integrity 6.1 Data loss at Power off The drive retains recorded information under all non-write operations. No more than one sector can be lost by power down during write operation while write cache is dis- abled. Power off during write operations may make an incomplete sector which will report hard data error when read.
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  • Page 35: File Organization

    7.0 File Organization 7.1 File format When the drive is shipped from IBM manufacturing it satisfies the sector continuity in the physical format by defect flagging strategy described in the following section in order to provide the maximum performance to us.
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  • Page 37: Defect Flagging Strategy

    8.0 Defect flagging strategy Media defects are remapped to the next available sector during the Format Process in manufacturing. The mapping from LBA to the physical locations is calculated by an internally maintained table. 8.1 Shipped format Data areas are optimally used. No extra sector is wasted as a spare throughout user data areas.
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  • Page 39: Specification

    9.0 Specification 9.1 Electrical interface 9.1.1 Connector location Refer to the following illustration to see the location of the connectors. Figure 19. Connector location 9.1.1.1 DC power connector The DC power connector is designed to mate with AMP (P/N 1-480424-0) using AMP pins (P/N 350078-4) (strip) or (P/N 61173-4) (loose piece) or their equivalents.

  • Page 40: Signal Definition

    9.1.2 Signal definition The pin assignments of interface signals are listed in the figure below: SIGNAL Type SIGNAL Type RESET- – – 3-state 3-state 3-state 3-state 3-state DD10 3-state 3-state DD11 3-state 3-state DD12 3-state 3-state DD13 3-state 3-state DD14 3-state 3-state DD15...
  • Page 41 DD00–DD15 DD00–DD15 are the 16-bit bi-directional data bus signal names. These lines connect the host and the drive. The lower 8 lines (DD00–07) are used for Register and ECC access. All 16 lines (DD00–DD15) are used for data transfer. Each line is a 3-state lines with 24 mA current sink capability.
  • Page 42 of a valid Execute Drive Diagnostics command for drive 1 to assert PDIAG-. Device 1 clears BSY before asserting PDIAG- and PDIAG- is used to indicate that Device 1 has passed its diagnostics and is ready to post status. If DASP- was not asserted by Device 1 during reset initialization, Device 0 shall post its own status immediately after it completes diagnostics and clear the Device 1 Status register to 00h.

  • Page 43: Interface Logic Signal Levels

    DDMARDY- (Ultra DMA) This signal is used only for Ultra DMA data transfers between the host and the drive. DDMARDY- is a flow control signal for Ultra DMA data out bursts. This signal is held asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out transfers.

  • Page 44: Pio Timings

    9.1.5 PIO timings The PIO cycle timings meet Mode 4 of the ATA/ATAPI-5 description. CS0-,CS1- DA0-2 DIOR-, DIOW- Write data DD00-DD15 Read data DD00-DD15 t7(*) t8(*) IOCS16-(*) IORDY Minimum Maximum Parameter descriptions (ns) (ns) Cycle time – CS0- CS1-, DA00–02 valid to DIOR-, DIOW- setup –...

  • Page 45: Multiword Dma Timings

    9.1.6 Multiword DMA timings The Multiword DMA timing meets Mode 2 of the ATA/ATAPI-5 description. CS0-/CS1- DMARQ DMACK- DIOR-/DIOW- READ DATA WRITE DATA Parameter descriptions MIN. (ns) MAX. (ns) Cycle time – DIOR-, DIOW- asserted pulse width – DIOR- data access –...

  • Page 46: Ultra Dma Timings

    9.1.7 Ultra DMA timings The Ultra DMA timing meets Modes 0, 1, 2, 3, 4, and 5 of the Ultra DMA Protocol. 9.1.7.1 Initiating Read DMA DMARQ DMACK- tENV tACK STOP tACK tENV t2CYC HDMARDY- tZIORDY tCYC tCYC tDZSF DSTROBE tDVH tZAD tZAD...

  • Page 47: Figure 28. Ultra Dma Cycle Timings (Host Pausing Read)

    9.1.7.2 Host Pausing Read DMA DMARQ DMACK- STOP HDMARDY- tRFS DSTROBE MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 Signal names Parameter descriptions Strobe to ready response time – – – – – – – – – tRFS Ready to final strobe time –...

  • Page 48: Figure 29. Ultra Dma Cycle Timings-Host Terminating Read

    9.1.7.3 Host Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tRFS tIORDYZ DSTROBE DD00–DD15 xxxxxxxxxx xxx RD Data xxxxxxxxxxxxxxxxxx tZAH Host drives DD Device drives DD MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 Signal names Parameter descriptions tRFS Ready to final strobe time –...

  • Page 49: Figure 30. Ultra Dma Cycle Timings-Device Terminating Read

    9.1.7.4 Device Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tIORDYZ DSTROBE DD00–DD15 xxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxx Tzah Device drives DD Host drives DD MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 Signal names Parameter descriptions Time from strobe to stop –...

  • Page 50: Figure 31. Ultra Dma Cycle Timings-Initiating Write

    9.1.7.5 Initiating Write DMA DMARQ DMACK- tACK tENV STOP tZIORDY t2CYC HDMARDY- tACK tCYC tCYC DSTROBE DD00–DD15 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx WT Data WT Data WT Data Host drives DD MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 Signal Parameter descriptions names Unlimited interlock time –...

  • Page 51: Figure 32. Ultra Dma Cycle Timings-Device Pausing Write

    9.1.7.6 Device Pausing Write DMA DMARQ DMACK- STOP DDMARDY- tRFS HSTROBE MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 Signal names Parameter descriptions Strobe to ready response time – – – – – – – – – tRFS Ready to final strobe time –...

  • Page 52: Figure 33. Ultra Dma Cycle Timings-Device Terminating Write

    9.1.7.7 Device Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK tRFS HSTROBE DD00–DD15 xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx WT Data Host drives DD MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 Signal names Parameter descriptions tRFS Ready to final strobe time – –...

  • Page 53: Figure 34. Ultra Dma Cycle Timings-Host Terminating Write

    9.1.7.8 Host Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK HSTROBE DD00–DD15 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx Host drives DD MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 Signal names Parameter descriptions Time from strobe to stop – – – – – –...

  • Page 54: Addressing Of Registers

    9.1.8 Addressing of registers The host addresses the drive through a set of registers called the Task File. These registers are mapped into the I/O space. Two chip select lines (CS0- and CS1-) and three address lines (DA0-02) are used to select one of these registers, while a DIOR- or DIOW- is provided at the specified time.

  • Page 55: Jumper Settings

    9.1.10 Jumper settings 9.1.10.1 Jumper pin location Jumper pins Figure 36. Jumper pin location 9.1.10.2 Jumper pin identification Pin I Pin A DERA001.prz Pin B Figure 37. Jumper pin identifications Deskstar 60 GXP Hard disk drive specification...

  • Page 56: Figure 38. Jumper Pin Assignment

    There are four jumper settings as shown in the following sections: Normal use 15 heads 2 GB clip Auto spin disable Each category is exclusive. The pin assignment of the 9-pin jumper used to select "Device 0", "Device 1", "Cable Selection", and "Device 0 with Device 1 Present" is shown in the following illustration. The "Device 0"...

  • Page 57: Figure 39. Jumper Block Setting Position

    9.1.10.3 Jumper block setting position—normal use The following illustration shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device 0 with Device 1 Present. DEVICE 0 (Master) DEVICE 1 (Slave) CABLE SEL DEVICE 1 (Slave) Present Shipping Default Condition (DEVICE 0) Notes:...

  • Page 58: Figure 40. Jumper Block Setting Position-15 Head

    9.1.10.4 Jumper block setting position—15 head The positions of jumper blocks shown below is used to select Device 0 or Device 1, Cable Selection, or Device 0 with Device 1 Present, setting 15 logical heads instead of the default 16 logical head models. DEVICE 0 (Master) DEVICE 1 (Slave) CABLE SEL...

  • Page 59: Figure 41. Jumper Block Setting Position-2 Gb/32 Gb Clip

    9.1.10.5 Jumper block setting position—2GB/32GB clip The positions of the jumper blocks shown below are used to select Device 0 or Device 1, Cable Selection, and Device 0 with Device 1 Present, setting the drive capacity down either to 2 GB or 32 GB for compatibility purposes.

  • Page 60: Figure 42. Jumper Block Setting Postion-Power Up In Standby

    9.1.10.6 Jumper block setting position—power up in standby The jumpers positions shown in the following illustration are used for enabling power up in standby. DEVICE 0 (Master) DEVICE 1 (Slave) CABLE SEL DEVICE 1 (Slave) Present Notes: These jumper settings are used for limiting power supply current when multiple drives are used. 2.

  • Page 61: Environment

    9.2 Environment 9.2.1 Temperature and humidity Operating conditions Temperature 5 to 55°C Relative humidity 8 to 90% non-condensing Maximum wet bulb temperature 29.4°C non-condensing Maximum temperature gradient 15°C/Hour Altitude –300 to 3,048 m Shipping conditions Temperature –40 to 65°C Relative humidity 5 to 95% non-condensing Maximum wet bulb temperature 35°C non-condensing...

  • Page 62: Corrosion Test

    9.2.2 Corrosion test The hard disk drive shows no signs of corrosion inside or outside of hard drive assembly and is functional after being subjected to seven days of a 50°C temperature and 90% relative humidity. 9.3 DC power requirements The following voltage specifications apply at the drive power connector.

  • Page 63: Power Supply Generated Ripple At Drive Power Connector

    9.3.3 Power supply generated ripple at drive power connector DC Volts Maximum peak-to-peak ripple voltage Frequency range (mV p-p) (MHz) 0–10 0–10 Figure 47. Power supply generated ripple at drive power connector During drive start up and seeking a 12-Volt ripple is generated by the drive—this is referred to as dynamic loading.

  • Page 64: Energy Consumption Efficiency

    9.3.5 Energy consumption efficiency Model by capacity in GB Energy consumption efficiency (W/GB) 0.67 0.34 0.22 0.17 0.13 0.11 Figure Energy consumption efficiency Energy consumption efficiency is calculated as power consumption at idle average. The unit of measure for the energy consumption efficiency is given in Watt/Gigabyte (W/GB). 9.4 Reliability 9.4.1 Data integrity No more than one sector is lost at a power loss condition during a write operation when the write cache...

  • Page 65: Data Reliability

    9.4.6 Data reliability Probability of not recovering data is 1 in 10 bits read. ECC On-The-Fly correction: 1 Symbol : 8 bits 3 Interleave. 12 ECC's are embedded into each interleave. 15 Symbols—5 Symbols per each interleave—for On The Fly correction This implementation always recovers 5 random burst errors and a 113 bits continuous burst error.

  • Page 66: Mounting Holes

    9.5.2 Mounting holes (6X) Max. penetration 4.5 mm Side View I/F Connector Bottom View (4X) Max. penetration 4.0 mm Dimension reference number Dimension 41.28 ± 0.5 44.45 ± 0.2 95.25 ± 0.2 6.35 ± 0.2 28.5 ± 0.5 60.0 ± 0.2 41.6 ±...

  • Page 67: Connector And Jumper Description

    Consult with your IBM Corporation distribution representative if your mounting application may possibly be considered out of compliance with this specification. When performing any drive level vibration and shock test, mount the drive to the table using the bottom four screws.

  • Page 68: Vibration And Shock

    9.6.1 Operating vibration 9.6.1.1 Random vibration The hard disk drive meets IBM Standard C-S 1-9711-002 (1990-03) for the V5L applied to the horizontal direction and V4 applied to the vertical direction. The test consists of 30 minutes of random vibration using the power spectral density (PSD) levels shown in the following table.

  • Page 69: Operating Shock

    3 minutes dwell at two major resonances 9.6.3 Operating shock The hard disk drive meets IBM Standard C-S 1-9711-007 for the S5 product classification. The drive meets the following criteria while operating in respective conditions described in the following bullet list. The shock test consists of ten shocks inputs in each axis and in each direction for a total of 60.

  • Page 70: Rotational Shock

    9.6.4.2 Sinusoidal shock wave The shape is approximately a half-sine pulse. The following table shows the maximum acceleration level and duration. Acceleration level (G) Duration (ms) 75 (all models) (3 disks) (1 disk) (2 disks) Figure 55. Sinusoidal shock wave 9.6.5 Rotational shock All shock inputs shall be applied around the actuator pivot axis.

  • Page 71: Identification-Labels

    The following labels are affixed to every drive shipped from the drive manufacturing location in accordance with the appropriate hard disk drive assembly drawing. • A label containing the IBM logo, the IBM part number, and the statement “Made by IBM Japan Ltd.”, or IBM equivalent.

  • Page 72: Flammability

    EMC requirements: The United States Federal Communications Commission (FCC) Rules and Regulations (Class B), Part 15. The IBM Corporate Standard C-S 2-0001-026 (A 6 dB buffer shall be maintained on the emission requirements).

  • Page 73: Ce Mark

    The product is declared to be in conformity with requirements of the following EC directives under the sole responsibility of Yamato Lab, IBM Japan Ltd. or IBM United Kingdom Ltd. Council Directive 89/336/EEC on the approximation of laws of the Member States relating to electromagnetic compatibility.
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  • Page 75: Part 2. Interface Specification

    Part 2. Interface specification Deskstar 60 GXP Hard disk drive specification...
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  • Page 77: General

    10.0 General Introduction 10.1 This specification describes the host interface of the IC35L0xxAVER07-0. The interface conforms to the Working Document of Information Technology - AT Attachment with Packet Interface Extension (ATA/ATAPI-5), Revision 3, dated 29 February 2000, with certain limitations described in Section 11.0 , "Deviations From Standard"...
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  • Page 79: Deviations From Standard

    11.0 Deviations from standard The device conforms to the referenced specifications with the following deviations: Check Power Mode. Check Power Mode command returns FFh to Sector Count Register when the device is in Idle mode. This command does not support 80h as the return value. Hard Reset.
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  • Page 81: Registers

    12.0 Registers Addresses Functions CS0– CS1– READ (DIOR–) WRITE (DIOW–) Not used Data bus high impedance Addresses Control block registers Not used Data bus high impedance Not used Data bus high impedance Alternate Status Device Control Device Address Not used Addresses Command block registers Data...

  • Page 82: Alternate Status Register

    12.1 Alternate Status Register Alternate Status Register DSC/ SERV Figure 59. Alternate Status Register This register contains the same information as the Status Register. The only difference is that reading this register does not imply interrupt acknowledge or clear a pending interrupt. See Section 12.13, "Status Register"...

  • Page 83: Data Register

    12.5 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide.

  • Page 84: Device/Head Register

    -DS1 -Drive Select 1. Drive select bit for Device 1, active low. DS1=0 when Device 1 (slave) is selected and active. -DS0 -Drive Select 0. Drive select bit for Device 0, active low. DS0=0 when Device 0 (master) is selected and active. 12.8 Device/Head Register Device/Head Register Figure 62.

  • Page 85: Features Register

    Bit Definitions ICRCE Interface CRC Error. CRC=1 indicates a CRC error has occurred on the data bus during (CRC) Ultra-DMA transfer. Uncorrectable Data Error. UNC=1 indicates an uncorrectable data error has been encountered. IDNF (IDN) ID Not Found. IDN=1 indicates the ID field of the requested sector could not be found. ABRT Aborted Command.

  • Page 86: Status Register

    12.13 Status Register Status Register DSC/ DRDY CORR SERV Figure 64. Status Register This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command. If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge.
  • Page 87 Error. ERR=1 indicates that an error occurred during execution of the previous command. The Error Register should be read to determine the error type. The device sets ERR=0 when the next command is received from the host. Deskstar 60 GXP Hard disk drive specification...
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  • Page 89: General Operation

    13.0 General operation 13.1 Reset response There are three types of resets in ATA: Power On Reset (POR) The device executes a series of electrical circuitry diagnostics, spins up the HDA, tests speed and other mechanical parametrics, and sets default values. Hard Reset (Hardware Reset) RESET- signal is negated in ATA Bus.

  • Page 90: Register Initialization

    13.2 Register initialization Register Default Value Error Diagnostic Code Sector Count Sector Number Cylinder Low Cylinder High Device/Head Status Alternate Status Figure 66. Default Register Values After power on, hard reset, or software reset, the register values are initialized as shown in the following figure.

  • Page 91: Diagnostic And Reset Considerations

    13.3 Diagnostic and Reset considerations For each Reset and Execute Device Diagnostic the diagnostic is done as follows: Power On Reset DASP- is read by Device 0 to determine if Device 1 is present. If Device 1 is present, Device 0 must read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error.

  • Page 92: Sector Addressing Mode

    13.4 Sector Addressing Mode All addressing of data sectors recorded on the device's media is by a logical sector address. The logical CHS address for all models is different from the actual physical CHS location of the data sector on the disk media.

  • Page 93: Overlapped And Queued Feature

    13.5 Overlapped and queued feature Overlap allows devices to perform a bus release so that the other device on the bus may be used. To perform a bus release the device clears both DRQ and BSY to zero. When selecting the other device during overlapped operations, the host shall disable interrupts via the nIEN bit on the currently selected device before writing the Device/Head register to select the other device.

  • Page 94: Power Management Feature

    13.6 Power management feature The power management feature set permits a host to modify the behavior of a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enable a device to implement low power consumption modes. The drive implements the following set of functions: A Standby timer Idle command...

  • Page 95: Interface Capability For Power Modes

    13.6.4 Interface capability for power modes Each power mode affects the physical interface as defined in the following table. Mode Interface active Media Active Active Idle Active Standby Inactive Sleep Inactive Figure 69. Power conditions Ready (RDY) is not a power condition. A device may post ready at the interface even though the media may not be accessible.

  • Page 96: Threshold Exceeded Condition

    13.7.4 Threshold Exceeded Condition If one or more attribute values—whose Pre-failure bit of their status flag is set—are less than or equal to their corresponding attribute thresholds, then the device reliability status is negative indicating an impending degrading or faulty condition. 13.7.5 S.M.A.R.T.

  • Page 97: Security Mode

    13.8.1 Security mode The following security modes are provided: Device Locked mode The device disables media access commands after power on. Media access commands are enabled by either a security unlock command or a security erase unit command. Device Unlocked mode The device enables all commands.

  • Page 98: Figure 70. Initial Setting

    13.8.4.2 User Password setting When a User Password is set, the device will automatically enter lock mode the next time the device is powered on. (Ref.) <Setting password> <No setting password> Set password with user Password Normal operation Normal operation Power off Power off Device unlocked mode...

  • Page 99: Figure 71. Usual Operation

    13.8.4.3 Operation from POR after User Password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed. Device Locked mode Unlock CMD Erase Prepare Non-media access Media Access Command (*1) Command (*1) Erase Unit...

  • Page 100: Figure 72. Password Lost

    13.8.4.4 User Password Lost If the User Password is forgotten and High level security is set, the system user can not access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.

  • Page 101: Command Table

    13.8.5 Command table This table shows the response of the device to commands when the Security Mode Feature Set (Device lock function) is enabled. Command Locked Mode Unlocked Mode Frozen Mode Check Power Mode Executable Executable Executable Execute Device Diagnostic Executable Executable Executable...

  • Page 102: Host Protected Area Function

    Command Locked Mode Unlocked Mode Frozen Mode Standby Executable Executable Executable Standby Immediate Executable Executable Executable Write Buffer Executable Executable Executable Write DMA (w/o retry) Command aborted Executable Executable Write DMA (w/retry) Command aborted Executable Executable Write DMA Queued Command aborted Executable Executable Write Long (w/o retry)

  • Page 103: Security Extensions

    a) Issue a Read Native Max Address command to get the real device maximum LBA. Returned value shows that the native device maximum LBA is 12,692,735 (C1ACFFh) regardless of the current setting. b) Make the entire device accessible including the protected area by setting device maximum LBA to 12,692,735 (C1ACFFh) via Set Max Address command.

  • Page 104: Seek Overlap

    13.10 Seek Overlap Each drive model provides an accurate seek time measurement method. The seek command is usually used to measure the device seek time by accumulating the execution time for a number of seek commands. With the typical implementation of the seek command this measurement must include the device and host command overhead.

  • Page 105: Write Cache Function

    13.11 Write cache function Write cache is a performance enhancement whereby the device reports the completion of the write command—Write Sectors, Write Multiple, and Write DMA—to the host as soon as the device has received all of the data into its buffer. The device assumes the responsibility of subsequently writing the data onto the disk.

  • Page 106: Recovered Read Errors

    13.13.3 Recovered read errors When a read operation for a sector has failed once and then has recovered at the specific ERP step, this sector of data is reallocated automatically. A media verification sequence may be run prior to the relocation according to the predefined conditions.

  • Page 107: Automatic Acoustic Management Feature Set (Aam)

    13.16 Automatic Acoustic Management feature set (AAM) This feature set allows the host to select an acoustic management level. The acoustic management level may range from the lowest acoustic emanation setting of 01h to the maximum performance level of FEh. Device performance and acoustic emanation may increase with increasing acoustic management levels.

  • Page 108: Identify Device Data

    Disable Address Offset Feature removes the address offset and sets the size of the drive reported by the Identify Device command back to the size specified in the last nonvolatile Set Max Address command. Before Enable Address Offset Mode A reserved area has been created using a non-volatile Set Max command. Non-Accessible Accessible (Sytem reserved...

  • Page 109: Command Protocol

    14.0 Command Protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check if BSY=1, and should proceed no further unless and until BSY=0.

  • Page 110: Pio Data Out Commands

    4. For the Read Long command: a. The device sets BSY=1 and prepares for data transfer. b. When the sector of data is available for transfer to the host, the device sets BSY=0, sets DRQ=1, and interrupts the host. c. In response to the interrupt the host reads the Status Register. d.
  • Page 111 Execution includes the transfer of one or more 512 byte (>512 bytes on Write Long) sectors of data from the host to the device. 1. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head Registers. 2.

  • Page 112: Non-Data Commands

    14.3 Non-data commands These commands are: Check Power Mode Execute Device Diagnostic Flush Cache Idle Idle Immediate Initialize Device Parameters Read Native Max Address Read Verify Sectors Recalibrate Security Erase Prepare Security Freeze Lock Seek Set Features Set Max Address Set Max Lock command Set Max Freeze Lock command Set Multiple Mode...

  • Page 113: Dma Commands

    14.4 DMA commands DMA commands are: Read DMA Write DMA Data transfers using DMA commands differ in two ways from PIO transfers: data transfers are performed using the slave DMA channel no intermediate sector interrupts are issued on multisector commands Initiation of the DMA transfer commands is identical to the Read Sector or Write Sector commands except that the host initializes the slave-DMA channel prior to issuing the command.
  • Page 114 e. The device clears BSY. 2. Data Transfer and Command Completion If the device is ready for data transfer (REL is cleared) a. The host transfers the data for the command identified by the Tag number using the DMA transfer protocol currently in effect.

  • Page 115: Command Descriptions

    15.0 Command descriptions Code Binary Code Bit Protocol Command (Hex) 7 6 5 4 3 2 1 0 Check Power Mode 1 1 1 0 0 1 0 1 Check Power Mode* 1 0 0 1 1 0 0 0 Execute Device Diagnostic 1 0 0 1 0 0 0 0 Flush Cache...

  • Page 116: Figure 76. Command Set (2 Of 2)

    Code Binary Code Bit Protocol Command (Hex) 7 6 5 4 3 2 1 0 S.M.A.R.T. Execute Off-line Data Collection 1 0 1 1 0 0 0 0 S.M.A.R.T. Read Attribute Values 1 0 1 1 0 0 0 0 S.M.A.R.T.

  • Page 117: Figure 77. Command Set-Subcommand

    Feature Command Command (Subcommand) Register Code (Hex) (Hex) S.M.A.R.T. Function S.M.A.R.T. Read Attribute Values S.M.A.R.T. Read Attribute Thresholds S.M.A.R.T. Enable/Disable Attribute Autosave S.M.A.R.T. Save Attribute Values S.M.A.R.T. Execute Off-line Data Collection S.M.A.R.T. Read Log S.M.A.R.T. Write Log S.M.A.R.T. Enable Operations S.M.A.R.T.
  • Page 118 Indicates that the hex character is not used. Indicates that the bit is not used. Input Registers Indicates that the bit is always set to zero. Indicates that the bit is always set to one. Head number. Indicates that the head number part of the Device/Head Register is an input parameter and will be set by the device.

  • Page 119: Check Power Mode (E5H/98H)

    15.1 Check Power Mode (E5h/98h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 120: Execute Device Diagnostic (90H)

    15.2 Execute Device Diagnostic (90h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 121: Flush Cache (E7H)

    15.3 Flush Cache (E7h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...

  • Page 122: Format Track (50H)

    15.4 Format Track (50h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...
  • Page 123 Input parameters from the device Sector Number In LBA mode this register specifies current LBA address bits 0–7. (L=1) Cylinder High/Low In LBA mode this register specifies current LBA address bits 8–15 (Low), 16–23 (High) In LBA mode this register specifies current LBA address bits 24–27. (L=1) Error The Error Register.

  • Page 124: Format Unit (F7H)

    15.5 Format Unit (F7h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 125: Identify Device (Ech)

    15.6 Identify Device (ECh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 126: Figure 84. Identify Device Information (1 Of 6)

    The Identify Device command requests the device to transfer configuration information to the host. The device will transfer a sector to the host containing the information described in the following figure. In the following table the bullet symbol (•) means the word is for vendor specific use. Word Content Description...

  • Page 127: Figure 84. Identify Device Information (2 Of 6)

    Word Content Description 400xH Capabilities, bit assignments: 15-14(=01) Word 50 is valid 13– 1(=0) Reserved Minimum value of Standby timer (=0) less than 5 minutes (=1) equal to or greater than 5 minutes 0200H PIO data transfer cycle timing mode 0200H DMA data transfer cycle timing mode Refer Word 62 and 63...

  • Page 128: Figure 84. Identify Device Information (3 Of 6)

    Word Content Description 00xxH Queue depth 15- 5 Reserved 4- 0 Maximum queue depth 76-79 0000H Reserved 003CH Major version number 15- 0 (=3C)ATA-2, ATA-3, ATA/ATAPI-4 and ATA/ATAPI-5 0015H Minor version number 15- 0 (=15)ATA/ATAPI-5 X3T13 1321D 74EBH Command set supported 15(=0) Reserved 14(=1)

  • Page 129: Figure 84. Identify Device Information (4 Of 6)

    Word Content Description xxxxH Command set/feature enabled Reserved NOP command READ BUFFER command WRITE BUFFER command Reserved Host Protected Area feature set DEVICE RESET command SERVICE interrupt RELEASE interrupt LOOK AHEAD WRITE CACHE PACKET Command feature set Power management feature set Removable feature set Security feature set S.M.A.R.T.

  • Page 130: Figure 84. Identify Device Information (5 Of 6)

    Word Content Description xxxxH Time required for Security Erase Unit completion Time = value * 2 (minutes) 0000H Time required for Enhanced security erase completion 0000H Current advanced power management value FFFEH Master Password Revision Code xxxxH Hardware reset result. Bit assignments 15-14 (=01) Word 93 is valid CBLID- status...

  • Page 131: Figure 84. Identify Device Information (6 Of 6)

    Word Content Description xxxxH Current Set Feature Option. Bit assignments 15- 4 Reserve Auto reassign 1= Enable Reverting 1= Enable Read Look-ahead 1= Enable Write Cache 1= Enable 130-159 xxxxH Reserved 160-254 0000H Reserved xxA5H 15–8 Checksum. This value is the two's complement of the sum of all bytes in byte 0 through 510 7–0 (A5) Signature Figure 84.

  • Page 132: Idle (E3H/97H)

    15.7 Idle (E3h/97h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature - - - - - - - - Error...
  • Page 133 Output parameters to the device Sector Count Time-out Parameter. If it is zero, the automatic power down sequence is disabled. If it is non-zero, then the automatic power down sequence is enabled. The time-out interval is shown below: Value Time-out ------- ------------------------ Timer disabled...

  • Page 134: Idle Immediate (E1H/95H)

    15.8 Idle Immediate (E1h/95h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...

  • Page 135: Initialize Device Parameters (91H)

    15.9 Initialize Device Parameters (91h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature - - - - - - - -...

  • Page 136: Nop (00H)

    15.10 NOP (00h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature V V V V V V V V Error...

  • Page 137: Read Buffer (E4H)

    15.11 Read Buffer (E4h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...

  • Page 138: Read Dma (C8H/C9H)

    15.12 Read DMA (C8h/C9h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature - - - - - - - -...
  • Page 139 The head number of the first sector to be transferred. (L=0) In LBA mode this register specifies LBA bits 24–27 to be transferred. (L=1) The retry bit. If it is set to one, then retries are disabled. Input parameters from the device Sector Count The number of requested sectors not transferred.

  • Page 140: Read Dma Queued (C7H)

    15.13 Read DMA Queued (C7h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 141 Input parameters from the device on bus release Sector Count Bits 7–3 (Tag) contain the Tag of the command being bus released. Bit 2 (REL) is set to one. Bit 1 (I/O) is cleared to zero. Bit 0 (C/D) is cleared to zero. Sector Number, Cylinder High/low, H n/a.

  • Page 142: Read Long (22H/23H)

    15.14 Read Long (22h/23h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...
  • Page 143 The retry bit. If set to one, then retries are disabled. Input parameters from the device Sector Count The number of requested sectors not transferred. Sector Number The sector number of the transferred sector. (L=0) In LBA mode this register contains current LBA bits 0–7. (L=1) Cylinder High/Low The cylinder number of the transferred sector.

  • Page 144: Read Multiple (C4H)

    15.15 Read Multiple (C4h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...
  • Page 145 Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 0–7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 8–15 (Low), 16–23 (High). (L=1) The head number of the last transferred sector.

  • Page 146: Read Native Max Address (F8H)

    15.16 Read Native Max Address (F8h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 147: Read Sectors (20H/21H)

    15.17 Read Sectors (20h/21h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...
  • Page 148 Input parameters from the device Sector Count The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 0–7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 149: Read Verify Sectors (40H/41H)

    15.18 Read Verify Sectors (40h/41h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 150 Input parameters from the device Sector Count The number of requested sectors not verified. This will be zero, unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains current LBA bits 0–7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 151: Recalibrate (1Xh)

    15.19 Recalibrate (1xh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error - - - - - - - -...

  • Page 152: Security Disable Password (F6H)

    15.20 Security Disable Password (F6h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 153: Security Erase Prepare (F3H)

    15.21 Security Erase Prepare (F3h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 154: Security Erase Unit (F4H)

    15.22 Security Erase Unit (F4h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature - - - - - - - -...

  • Page 155: Figure 102. Erase Unit Information

    Word Description Control Word bit 0 : Identifier (1- Master, 0- User) bit 1 : Erase mode (1- Enhanced, 0- Normal) Enhanced mode is not supported bit 2-15: Reserved 01-16 Password ( 32 bytes ) 17-255 Reserved Figure 102. Erase Unit Information Identifier Zero indicates that the device should check the supplied password against the user password stored internally.

  • Page 156: Security Freeze Lock (F5H)

    15.23 Security Freeze Lock (F5h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature - - - - - - - -...

  • Page 157: Security Set Password (F1H)

    15.24 Security Set Password (F1h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 158: Figure 105. Security Set Password Information

    Word Description Control Word bit 0 : Identifier (1- Master, 0- User) bit 1-7 : Reserved bit 8 : Security level (1- Maximum, 0- High) bit 9-15 : Reserved 01-16 Password ( 32 bytes ) Master Password Revision Code Valid if Word 0 bit 0 = 1 18-255 Reserved Figure 105.

  • Page 159: Security Unlock (F2H)

    15.25 Security Unlock (F2h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...

  • Page 160: Seek (7Xh)

    15.26 Seek (7xh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error - - - - - - - -...

  • Page 161: Service (A2H)

    15.27 Service (A2h) Command Block Output Registers Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Feature - - - - - - - - Sector Count - - - - - - - - Sector Number - - - - - - - - Cylinder Low...

  • Page 162: Set Features (Efh)

    15.28 Set Features (EFh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...
  • Page 163 The Set Feature command is to establish the following parameters which affect the execution of certain features as shown in the following table. ABT will be set to 1 in the Error Register if the Feature register contains any undefined values. Command feature Destination code for this command Enable write cache...

  • Page 164: Set Transfer Mode

    15.28.1 Set Transfer mode When Feature register is 03h (=Set Transfer mode), the Sector Count Register specifies the transfer mechanism. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. PIO Default Transfer Mode 00000 000 PIO Default Transfer Mode, Disable IORDY 00000 001...

  • Page 165: Set Max Address (F9H)

    15.29 Set Max Address (F9h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 166 Output parameters to the device Option bit for selection whether nonvolatile or volatile. B=0 is volatile condition. When B=1, MAX Address which is set by Set Max Address command is preserved by POR. When B=0, MAX Address which is set by Set Max Address command will be lost by POR.

  • Page 167: Set Max Set Password (Feature = 01H)

    15.29.1 Set Max Set Password (Feature = 01h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data – – – – – – – – Data –...

  • Page 168: Set Max Lock (Feature = 02H)

    15.29.2 Set Max Lock (Feature = 02h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 169: Set Max Unlock (Feature = 03H)

    15.29.3 Set Max Unlock (Feature = 03h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature 0 0 0 0 0 0 1 1...

  • Page 170: Set Max Freeze Lock (Feature = 04H)

    15.29.4 Set Max Freeze Lock (Feature = 04h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 171: Set Multiple (C6H)

    15.30 Set Multiple (C6h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...

  • Page 172: Sleep (E6H/99H)

    15.31 Sleep (E6h/99h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error - - - - - - - -...

  • Page 173: Function Set (B0H)

    15.32 S.M.A.R.T. Function Set (B0h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 174: Read Attribute Values (Subcommand D0H)

    In order to select a subcommand the host must write the subcommand code to the Features Register of the device before issuing the S.M.A.R.T. Function Set command. The subcommands and their respective codes are listed below. Code Subcommand S.M.A.R.T. Read Attribute Values S.M.A.R.T.

  • Page 175: Save Attribute Values (Subcommand D3H)

    The SMART Disable Operations subcommand disables the Autosave feature along with the S.M.A.R.T. operations of the device. Upon receipt of the subcommand from the host the device asserts BSY, enables or disables the Autosave feature, clears BSY, and asserts INTRQ. 15.32.4 S.M.A.R.T.

  • Page 176: Read Log Sector (Subcommand D5H)

    15.32.6 S.M.A.R.T. Read Log Sector (Subcommand D5h) This command returns the specified log sector contents to the host. The 512 bytes data are returned at a command and the Sector Count value shall be set to one. The Sector Number shall be set to specify the log sector address. Log sector address Content Type...

  • Page 177: Return Status (Subcommand Dah)

    15.32.10 S.M.A.R.T. Return Status (Subcommand DAh) This command is used to communicate the reliability status of the device upon the request of the host. Upon receipt of the S.M.A.R.T. Return Status subcommand the device saves any updated Pre-failure type Attribute Values to the reserved sector and compares the updated Attribute Values to the Attribute Thresholds.

  • Page 178: Device Attributes Data Structure

    15.32.12 Device Attributes Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values subcommand. All multibyte fields shown in these data structures are in byte ordering—that is the least significant byte occupies the lowest numbered byte address location in the field.

  • Page 179: Figure 123. Individual Attribute Data Structure

    15.32.12.2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure. Description Byte Offset Attribute ID Number (01h to FFh) Status flags Attribute Value (valid values from 01h to FDh) Vendor Specific Total Bytes Figure 123.
  • Page 180 Status Flag definitions Definition Pre-failure/advisory bit An attribute value less than or equal to its corresponding attribute threshold indicates an advisory condition where the usage or age of the device has exceeded its intended design life period. An attribute value less than or equal to its corresponding attribute threshold indicates a pre-Failure condition where imminent loss of data is being predicted.

  • Page 181: Total Time In Seconds To Complete Off-Line Data Collection Activity

    15.32.12.4 Self-test execution status Definition Percent Self-test remaining. 0–3 An approximate percentage of the self-test routine remaining until completion; given in ten percent increments. Valid values are 0 through 9 4–7 Current Self-test execution status The self-test routine completed without error or has not been run The self-test routine aborted by the host The self-test routine interrupted by the host with a hard or soft reset The device was unable to complete the self-test routine due to a fatal error or...

  • Page 182: Capability

    15.32.12.7 S.M.A.R.T. capability This word of bit flags describes the S.M.A.R.T. capabilities of the device. The device will return 03h indicating that the device will save its Attribute Values prior to going into a power saving mode and supports the S.M.A.R.T. ENABLE/DISABLE ATTRIBUTE AUTOSAVE command. Definition Pre-power mode attribute saving capability If bit = 1, the device will save its Attribute Values prior to going into a power saving mode...

  • Page 183: Device Attribute Thresholds Data Structure

    15.32.13 Device Attribute Thresholds Data Structure The following defines the 512 bytes that make up the Attribute Threshold information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Thresholds. All multibyte fields shown in these data structures are in byte ordering—that is the least significant byte occupies the lowest numbered byte address location in the field.

  • Page 184: Error Log Sector

    15.32.13.4 Attribute Threshold These values are preset at the factory and are not intended to be changeable. 15.32.13.5 Data Structure Checksum The Data Structure Checksum is the two's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data structure.

  • Page 185: Figure 128. Error Log Data Structure

    15.32.14.4 Error log data structure Data format of error data structure is shown in the following table. Description Byte Offset 1st command data structure 2nd command data structure 3rd command data structure 4th command data structure 5th command data structure Error data structure Figure 128.

  • Page 186: Figure 130. Error Data Structure

    Error data structure: Data format of error data structure is shown in the following table. Description Byte Offset Reserved Error register Sector count register Sector number register Cylinder Low register Cylinder High register Device/Head register Status register Extended error data (vendor specific) State Life time stamp (hours)

  • Page 187: Self-Test Log Data Structure

    15.32.15 Self-test log data structure The following figure defines the 512 bytes that make up the Self-test log sector. All multibyte fields shown in these data structures are in byte ordering. Description Byte Offset Data structure revision Self-test number n*18h+02h Self-test execution status n*18h+03h Life time power on hours...

  • Page 188: Error Reporting

    15.32.16 Error reporting The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device. Status Error Error condition Register Register A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being loaded into the Cylinder High and Cylinder Low registers.

  • Page 189: Standby (E2H/96H)

    15.33 Standby (E2h/96h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error - - - - - - - -...
  • Page 190 Output Parameters To The Drive Sector Count This is a Time-out Parameter. If the Sector Count is 0, then the automatic power down sequence is disabled. If the Sector Count is non-zero, then the automatic power down sequence is enabled. The time-out intervals are shown as follows: Value Time-out --------...

  • Page 191: Standby Immediate (E0H/94H)

    15.34 Standby Immediate (E0h/94h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...

  • Page 192: Write Buffer (E8H)

    15.35 Write Buffer (E8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data Feature...

  • Page 193: Write Dma (Cah/Cbh)

    15.36 Write DMA (CAh/CBh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data Feature...
  • Page 194 The retry bit. If set to 1, then retries are disabled. It is ignored, when write cache is enabled. (Ignoring the retry bit is in violation of ATA-2.) Input parameters from the device Sector Count The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs.

  • Page 195: Write Dma Queued (Cch)

    15.37 Write DMA Queued (CCh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
  • Page 196 Input parameters from the device on bus release Sector Count Bits 7–3 (Tag) contain the Tag of the command being released to the bus. Bit 2 (REL) is set to one. Bit 1 (I/O) is cleared to zero. Bit 0 (C/D) is cleared to zero. Sector Number, Cylinder High/Low, H n/a.

  • Page 197: Write Long (32H/33H)

    15.38 Write Long (32h/33h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...
  • Page 198 This parameter represents the retry bit. If set to one, then retries are disabled. Input parameters from the device Sector Count This parameter represents the number of requested sectors not transferred. Sector Number This parameter represents the sector number of the sector to be transferred. (L=0) In LBA mode this register contains current LBA bits 0–7.

  • Page 199: Write Multiple (C5H)

    15.39 Write Multiple (C5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data Feature...
  • Page 200 Input Parameters From The Device Sector Count This parameter represents the number of requested sectors not transferred. This number will be zero—unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode this register contains the current LBA bits 0–7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 201: Write Sectors (30H/31H)

    15.40 Write Sectors (30h/31h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature Error...
  • Page 202 Input parameters from the device Sector Count This parameter represents the number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs. Sector Number The sector number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 0–7. (L=1) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 203: Appendix

    Appendix I. Commands Support Coverage Following table is provided to facilitate the understanding of DTLA-3XXXXX command support coverage comparing to the ATA-5 defined command set. The column entitled "Implementation" shows the capability of DTLA-3XXXXX for those commands. Command Command Implementation ATA-5 Category Code Name...

  • Page 204: Figure 141. Command Coverage (2 Of 2)

    Command Command Implementation ATA-5 Command Type Code Name for DTLA-3XXXXX WRITE DMA (w/ retry) Mandatory WRITE DMA (w/o retry) Obsoleted WRITE DMA QUEUED Optional CFA WRITE MULTIPLE W/O ERASE Optional – (7) GET MEDIA STATUS Optional (7) MEDIA LOCK Optional (7) MEDIA UNLOCK Optional (7) STANDBY IMMEDIATE...

  • Page 205: Set Features Command Support Coverage

    II. SET FEATURES Command Support Coverage The following table provides a list of Feature Registers, Feature Names, and implementation for the DTLA-3XXXXX models. The "Implementation" column indicates with a "Yes" or "No" whether or not the DTLA-3XXXXX models have the capability of executing the command in comparison to the ATA/ATAPI-5 defined command set.
  • Page 206 This page intentionally left blank.

  • Page 207: Index

    Index Drive ready time, 12 DRQ interval time, 30 Abbreviations used, 1 Acoustics, 56 Actuator, 7 Address Offset, 93 ECC On-The-Fly correction, 51 Addressing of HDD registers, 40 Electrical interface, 25 Advanced Power Management, 92 Electromagnetic compatibility, 58 Appendix A, 189 Energy consumption efficiency, 50 AT signal connector, 25 Equipment status, 19...
  • Page 208 Safety, 57 Sector Addressing Mode, 78 Non-data commands, 98 Security, 82 Seek Overlap, 90 SET FEATURES Command Support Coverage, Operating conditions, 47 Operating mode definition, 15 Shipped format, 17, 23 Shipping conditions, 47 Shock, 54 Signal definitions, 26 Password Lost, 86 Simple sequential access, 13 Passwords, 83 Single Track Seek Time, 12...
  • Page 209 IBM representative. Data subject to change without notice. References in this publication to IBM products, programs, or services do not imply that IBM intends to make them available in all countries in which IBM operates. Document # S07N-4780-04 Publication #2818...

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