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Bit 2: PCBB
0
1
•
Bits 1 and 0—Reserved bits: These bits always read 0. The write value should always be 0.
6.3
Operation
6.3.1
Flow of the User Break Operation
The flow from setting of break conditions to user break interrupt exception processing is described
below:
1.
The break addresses are set in the break address registers (BARA, BARB), the masked
addresses are set in the break address mask registers (BAMRA, BAMRB), the break data is
set in the break data register (BDRB), and the masked data is set in the break data mask
register (BDMRB). The breaking bus conditions are set in the break bus cycle registers
(BBRA, BBRB). The three groups of the BBRA and BBRB—CPU cycle/peripheral cycle
select, instruction fetch/data access select, and read/write select— are each set. No user break
interrupt will be generated if even one of these groups is set with 00. The respective
conditions are set in the bits of the registers of the BRCR.
2.
When the set conditions are satisfied, the UBC sends a user break interrupt request to the
interrupt controller. When conditions match up, the CPU condition match flags (CMFCA,
CMFCB) and peripheral condition match flags (CMFPA, CMFPB) for the respective channels
are set.
3.
The interrupt controller checks the user break interrupt's priority level. The user break
interrupt has priority level 15, so it is accepted only if the interrupt mask level in bits I3–I0 in
the status register (SR) is 14 or lower. When the I3–I0 bit level is 15, the user break interrupt
cannot be accepted but it is held pending until user break interrupt exception processing can
be carried out. Section 5, Interrupt Controller, describes the handling of priority levels in
greater detail.
4.
When the priority is found to permit acceptance of the user break interrupt, the CPU starts
user break interrupt exception processing.
5.
The appropriate condition match flag (CMFCA, CMHPA, CMFCB, CMFPB) can be used to
check if the set conditions match or not. The flags are set by the matching of the conditions,
but they are not reset. 0 must first be written to them before they can be used again.
108 Hitachi
Description
Places the channel B instruction fetch cycle break before instruction
execution (initial value).
Places the channel B instruction fetch cycle break after instruction
execution.
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