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Packed process data for inputs
The following indicates the assignment of the QJ71MT91 to the buffer memory and the data structure of the NZ2FT-MT
register.
Address
b15
(offset)
nH
NZ2FTS3-8DE
n+1H
-
n+2H
NZ2FTS1-16DE
n+3H
n+4H
NZ2FTS-60AD4
n+5H
n+6H
n+7H
-
n+8H
n+9H
n+AH
NZ2FTS-D62P2
n+BH
n+CH
n+DH
The structure of Packed process data for inputs is as follows.
• Process data of the input module is arranged in order of mounting position proximity to the NZ2FT-MT.
• The size of Packed process data of each I/O module depends on the I/O module. ( Page 323 Data width used by the I/
O module)
• There is no assignment for output modules.
• The I/O modules with the Packed process data size of 8 bits or less are assigned next to the previous I/O module.
• The I/O modules with the Packed process data size of 16 bits or more are assigned from the start of the next word.
• Process data of the NZ2FTS4-4DE uses only 4 bits of b0 to b3, and 4 bits of b4 to b7 are allocated for only the area.
QJ71MT91
...
b0
NZ2FTS4-4DE
NZ2FTS3-8DE
NZ2FTS3-8DE
NZ2FT-MT
b15
Address
0000H
NZ2FTS3-8DE
0001H
-
0002H
NZ2FTS1-16DE
0003H
0004H
NZ2FTS-60AD4
0005H
0006H
0007H
-
0008H
0009H
000AH
NZ2FTS-D62P2
000BH
000CH
000DH
11.8 Access to Process Data
...
b0
NZ2FTS4-4DE
NZ2FTS3-8DE
NZ2FTS3-8DE
11 NZ2FT-MT
333
11
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