Interrupt Response Time; Table 19.9 Interrupt Response Time - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Interrupt Response Time

The time from generation of an interrupt request until interrupt exception handling is performed

and fetching of the first instruction of the exception service routine is started (the interrupt

response time) is shown in table 19.9.

Time for priority decision and

SR mask bit comparison*

Wait time until end of

sequence being executed by

Time from interrupt exception

handling (save of SR and PC)

until fetch of first instruction of

exception handler is started

One cycle of internal clock supplied to CPU, etc.

Bcyc: One CKIO cycle

Latency of instruction

Note: * In the SH7750 and SH7750S including the case where the mask bit (IMASK) in SR is

changed, and a new interrupt is generated.

Number of States

1Icyc + 4Bcyc

1Icyc + 7Bcyc

S – 1 (≥ 0) ×

5Icyc + 4Bcyc

5Icyc + 7Bcyc

+ (S – 1)Icyc

1Icyc + 2Bcyc

S – 1 (≥ 0) ×

5Icyc + 2Bcyc

+ (S – 1)Icyc

Rev. 6.0, 07/02, page 771 of 986

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