Dram Interface - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Read-Strobe Negate Timing (Setting Only Possible in the SH7750R): When the SRAM

interface is used, timing for the negation of the strobe during read operations can be specified by

the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this

setting, see the description of the WCR3 register. When a byte control SRAM setting is made,

AnRDH should be cleared to 0.

TS1: Setup wait

Note: * When AnRDH is set to 1

Figure 13.13 SRAM Interface Read-Strobe Negate Timing

DRAM Interface

Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to

100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The

DRAM interface function can then be used to connect DRAM to the SH7750.

16, 32, or 64 bits can be selected as the interface data width for area 3 when bits DRAMTP2–0 are

set to 100, and 16 or 32 bits can be used for both area 2 and area 3 when bits DRAMTP2–0 are set

2-CAS 16-bit DRAMs can be connected, since CAS is used to control byte access.

(AnS = 1, AnW = 4, AnH = 2)

Tw: Access wait

TH1, TH2: Hold wait

Rev. 6.0, 07/02, page 395 of 986

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