Floating-Point Status/Control Register (Fpscr) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Floating-Point Status/Control Register (FPSCR)

Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001)

Note: —: Reserved. These bits are always read as 0, and should only be written with 0.

• FR: Floating-point register bank

FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1–

FPR15_BANK1 are assigned to XF0–XF15.

FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1–

FPR15_BANK1 are assigned to FR0–FR15.

• SZ: Transfer size mode

SZ = 0: The data size of the FMOV instruction is 32 bits.

SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).

• PR: Precision mode

PR = 0: Floating-point instructions are executed as single-precision operations.

PR = 1: Floating-point instructions are executed as double-precision operations (graphics

support instructions are undefined).

Do not set SZ and PR to 1 simultaneously; this setting is reserved.

[SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)

• DN: Denormalization mode

DN = 0: A denormalized number is treated as such.

DN = 1: A denormalized number is treated as zero.

• Cause: FPU exception cause field

• Enable: FPU exception enable field

• Flag: FPU exception flag field

FPU exception

FPU exception

enable field

FPU exception

22 21 20 19 18 17

Operation (V)

Rev. 6.0, 07/02, page 167 of 986

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