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(a) Serial execution: non-parallel-executable instructions
SHAD R0,R1
ADD
R2,R3
next
(b) Parallel execution: parallel-executable and no dependency
ADD
R2,R1
MOV.L @R4,R5
(c) Issue rate: multi-step instruction
AND.B#1,@(R0,GBR)
MOV
R1,R2
next
(d) Branch
BT/S L_far
ADD R0,R1
SUB R2,R3
BT/S L_far
ADD R0,R1
L_far
BT L_skip
ADD #1,R0
L_skip:
1 issue cycle
EX
I
D
NA
I
EX
D
NA
1 stall cycle
I
D
...
1 issue cycle
EX
I
D
NA
EX
I
D
MA
SX
I
D
MA
SX
D
NA
SX
D
I
4 stall cycles
EX
I
D
NA
EX
I
D
NA
EX
I
D
NA
2-cycle latency for I-stage of branch destination
EX
I
D
NA
I
EX
NA
D
1 stall cycle
I
D
...
EX
I
D
NA
—
—
I
D
I
D
...
No stall
Figure 8.3 Examples of Pipelined Execution
S
S
S
S
4 issue cycles
S
S
NA
S
SX
MA
S
D
A
i
D
E
I
...
S
S
S
S
S
S
—
Rev. 6.0, 07/02, page 207 of 986
EX-group SHAD and EX-group ADD
cannot be executed in parallel. Therefore,
SHAD is issued first, and the following
ADD is recombined with the next
instruction.
EX-group ADD and LS-group MOV.L can
be executed in parallel. Overlapping of
stages in the 2nd instruction is possible.
AND.B and MOV are fetched
simultaneously, but MOV is stalled due to
resource locking. After the lock is released,
MOV is refetched together with the next
instruction.
S
No stall occurs if the branch is not taken.
If the branch is taken, the I-stage of the
branch destination is stalled for the period
of latency. This stall can be covered with a
delay slot instruction which is not parallel-
executable with the branch instruction.
Even if the BT/BF branch is taken, the I-
stage of the branch destination is not
stalled if the displacement is zero.
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