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14.5.2
Pins in DDT Mode
Figure 14.24 shows the system configuration in DDT mode.
SH7750 Series
A25–A0, RAS, CAS, WE, DQMn, CKE
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
• DBREQ
DBREQ: Data bus release request signal for transmitting the data transfer request format (DTR
DBREQ
DBREQ
format) or a DMA request from an external device to the DMAC
If there is a wait for release of the data bus, an external device can have the data bus released
by asserting DBREQ. When DBREQ is accepted, the BSC asserts BAVL.
• BAVL
BAVL: Data bus D63–D0 release signal
BAVL
BAVL
Assertion of BAVL means that the data bus will be released two cycles later.
The SH-4 does not switch the data pins to output status for a total of three cycles: the cycle in
which the data bus is released and the cycles preceding and following it.
• TR
TR: Transfer request signal
TR
TR
Assertion of TR has the following different meanings.
In normal data transfer mode (channel 0), TR is asserted, and at the same time the DTR
format is output, two cycles after BAVL is asserted.
In the case of the handshake protocol without use of the data bus, asserting TR enables a
transfer request to be issued for the channel for which a transfer request was made
immediately before. This function can be used only when BAVL is not asserted two cycles
earlier.
In the case of direct data transfer mode (valid only for channel 2), a direct transfer request
can be made to channel 2 by asserting DBREQ and TR simultaneously.
/DREQ0
/DRACK0
/DREQ1
/DACK0
ID1, ID0/DRAK1, DACK1
CLK
D63–D0
Synchronous
DRAM
External device
Rev. 6.0, 07/02, page 547 of 986
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