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14.5.2
Pins in DDT Mode
Figure 14.24 shows the system configuration in DDT mode.
SH7750
A25–A0, RAS, CAS, WE, DQMn, CKE
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
• '%5(4
'%5(4: Data bus release request signal for transmitting the data transfer request format (DTR
'%5(4
'%5(4
format) or a DMA request from an external device to the DMAC
If there is a wait for release of the data bus, an external device can have the data bus released
by asserting '%5(4. When '%5(4 is accepted, the BSC asserts %$9/.
• %$9/
%$9/: Data bus D63–D0 release signal
%$9/
%$9/
Assertion of %$9/ means that the data bus will be released two cycles later.
• 75
75
75
75: Transfer request signal
Assertion of 75 has the following different meanings.
In normal data transfer mode (except channel 0), 75 is asserted, and at the same time the
DTR format is output, two cycles after %$9/ is asserted.
In the case of the handshake protocol without use of the data bus, asserting 75 enables a
transfer request to be issued for the channel for which a transfer request was made
immediately before. This function can be used only when %$9/ is not asserted two cycles
earlier.
In the case of direct data transfer mode (valid only for channel 2), a direct transfer request
can be made to channel 2 by asserting '%5(4 and 75 simultaneously.
Rev. 4.0, 04/00, page 476 of 850
/DREQ0
/DRACK0
/DREQ1
/DACK0
ID1, ID0/DRAK1, DACK1
CLK
D63–D0
Synchronous
DRAM
External device
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