Overview Of Areas - Hitachi SH7750 series Hardware Manual

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Overview of Areas

Space Divisions: The architecture of the SH7750 Series provides a 32-bit virtual address space.

The virtual address is divided into five areas according to the upper address value. External

address comprises a 29-bit address space, divided into eight areas.

The virtual address can be allocated to any external address by means of the memory management

unit (MMU). Details are given in section 3, Memory Management Unit (MMU). This section

describes the areas into which the external address is divided.

With the SH7750 Series, various kinds of memory or PC cards can be connected to the seven

areas of external address as shown in table 13.3, and chip select signals (&63–&69, &(5$, &(5%)

are output for each of these areas. &63 is asserted when accessing area 0, and &69 when accessing

area 6. When DRAM or synchronous DRAM is connected to area 2 or 3, signals such as 5$6,

&$6, RD/:5, and DQM are also asserted. When the PCMCIA interface is selected for area 5 or

6, &(5$, &(5% is asserted in addition to &68, &69 for the byte to be accessed.

Store queue area

Physical address

Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and

memory is mapped onto a fixed 29-bit external address.

2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be

mapped onto any external address using the TLB.

For details, see section 3, Memory Management Unit (MMU).

Figure 13.2 Correspondence between Virtual Address Space and External Memory Space

Store queue area

Virtual address

Area 7 (reserved area)

External memory

Rev. 4.0, 04/00, page 265 of 850

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