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13.1.3
Pin Configuration
Table 13.1 shows the BSC pin configuration.
Table 13.1 BSC Pins
Name
Address bus
Data bus
Data bus/port
Bus cycle start
Chip select 6–0
Read/write
Row address
strobe
Read/column
address strobe/
cycle frame
Data enable 0
Rev. 4.0, 04/00, page 260 of 850
Signals
I/O
A25–A0
O
D63–D52,
I/O
D31–D0
D51–D32/
I/O
PORT19–
PORT0
%6
O
&69–&63
O
RD/:5
O
5$6
O
5'/&$66/
O
)5$0(
:(3/&$63/
O
DQM0
Description
Address output
Data input/output
When port functions are used and DDT mode is
selected, input the DTR format. Otherwise, when
port functions are used, D60-D52 cannot be used
and should be left open.
When port functions are not used: data input/output
When port functions are used: input/output port
(input or output set for each bit by register)
Signal that indicates the start of a bus cycle
When setting synchronous DRAM interface:
asserted once for a burst transfer
For other burst transfers: asserted each data cycle
Chip select signals that indicate the area being
accessed
&68 and &69 are also used as PCMCIA &(4$ and
&(4%
Data bus input/output direction designation signal
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal
5$6 signal when setting DRAM/synchronous DRAM
interface
Strobe signal that indicates a read cycle
When setting synchronous DRAM interface: &$6
signal
When setting MPX interface: )5$0( signal
When setting synchronous DRAM interface:
selection signal for D7–D0
When setting DRAM interface: &$6 signal for
D7–D0
When setting MPX interface: high-level output
In other cases: write strobe signal for D7–D0
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