Table of Contents
Advertisement
13.3.15 Cooperation between Master and Slave
To enable system resources to be controlled in a harmonious fashion by master and slave, their
respective roles must be clearly defined. Before DRAM or synchronous DRAM is used,
initialization operations must be carried out. Responsibility must also be assigned when a standby
operation is performed to implement the power-down state.
The design of the SH7750 Series provides for all control, including initialization, refreshing, and
standby control, to be carried out by the master mode device. In a dual-processor configuration
using direct master/slave connection, all processing except direct access to memory is handled by
the master. In a combination of master mode and partial-sharing master mode, the partial-sharing
master mode processor performs initialization, refreshing, and standby control for the areas
connected to it, with the exception of area 2, while the master performs initialization of the
memory connected to it.
If the SH7750 Series is specified as the master in a power-on reset, it will not accept bus requests
from the slave until the %5(4 enable bit (BCR1.BREQEN) is set to 1.
To ensure that the slave processor does not access memory requiring initialization before use, such
as DRAM and synchronous DRAM, until initialization is completed, write 1 to the %5(4 enable
bit after initialization ends.
Before setting self-refresh mode in standby mode, etc., write 0 to the %5(4 enable bit to
invalidate the %5(4 signal from the slave. Write 1 to the %5(4 enable bit only after the master
has performed the necessary processing (refresh settings, etc.) for exiting self-refresh mode.
13.3.16 Notes on Usage
Refresh: Auto refresh operations stop when a transition is made to standby mode or deep-sleep
mode. If the memory system requires refresh operations, set the memory in the self-refresh state
prior to making the transition to standby mode or deep-sleep mode.
Bus Arbitration: On transition to standby mode or deep-sleep mode, the processor in master
mode does not release bus privileges. In systems performing bus arbitration, make the transition to
standby mode or deep-sleep mode only after setting the bus privilege release enable bit
(BCR1.BREQEN) to 0 for the processor in master mode. If the bus privilege release enable bit
remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or
deep-sleep mode.
Rev. 4.0, 04/00, page 418 of 850
Advertisement
Table of Contents
