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12.1
Overview
The SH7750 includes an on-chip 32-bit timer unit (TMU) comprising three 32-bit timer channels
(channels 0 to 2).
12.1.1
Features
The TMU has the following features.
• Auto-reload type 32-bit down-counter provided for each channel
• Input capture function provided in channel 2
• Selection of rising edge or falling edge as external clock input edge when external clock is
selected or input capture function is used
• 32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit
down-counter provided for each channel
• Selection of seven counter input clocks for each channel
External clock (TCLK), on-chip RTC output clock, five internal clocks (Pφ/4, Pφ/16, Pφ/64,
Pφ/256, Pφ/1024) (Pφ is the peripheral module clock)
• Each channel can also operate in module standby mode when the on-chip RTC output clock is
selected as the counter input clock; that is, timer operation continues even when the clock has
been stopped for the TMU.
Timer count operations using an external or internal clock are only possible when a clock is
supplied to the timer unit.
• Synchronous read operation
As the timer counters (TCNT) are serially modified 32-bit registers and the internal peripheral
module bus is 16 bits wide, there is a time difference when reading the upper 16 bits and lower
16 bits of TCNT. To prevent counter read value drift due to this time difference, a
synchronization circuit is provided that allows simultaneous reading of all 32 bits of the TCNT
data.
• Two interrupt sources
One underflow source (channels 0 to 2) and one input capture source (channel 2)
• DMAC data transfer request capability
On channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is
generated.
Section 12 Timer Unit (TMU)
Rev. 4.0, 04/00, page 241 of 850
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