Table of Contents
Advertisement
9.6
Module Standby Function
9.6.1
Transition to Module Standby Function
Setting the MSTP4–MSTP0 bits in the standby control register to 1 enables the clock supply to the
corresponding on-chip peripheral modules to be halted. Use of this function allows power
consumption in sleep mode to be further reduced.
In the module standby state, the on-chip peripheral module external pins retain their states prior to
halting of the modules, and most registers retain their states prior to halting of the modules.
Bit
4
MSTP6*
0
1
4
MSTP5*
0
1
MSTP4
0
1
MSTP3
0
1
MSTP2
0
1
MSTP1
0
1
MSTP0
0
1
Notes: 1. The register initialized is the same as in standby mode, but initialization is not
performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)).
2. The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime
Clock (RTC)).
3. Terminate DMA transfers prior to making the transition to module standby mode. If you
make a transition to module standby mode while DMA transfers are in progress, the
results of those transfers cannot be guaranteed.
4. SH7750S only
5. For details, see section 20.2, User Break Controller Stop Functions.
9.6.2
Exit from Module Standby Function
The module standby function is exited by clearing the MSTP4–MSTP0 bits to 0, or by a power-on
reset via the 5(6(7 pin or a power-on reset caused by watchdog timer overflow.
Description
SQ operates
Clock supplied to SQ is stopped
UBC operates
Clock supplied to UBC is stopped*
DMAC operates
Clock supplied to DMAC is stopped*
SCIF operates
Clock supplied to SCIF is stopped
TMU operates
Clock supplied to TMU is stopped, and register is initialized*
RTC operates
Clock supplied to RTC is stopped*
SCI operates
Clock supplied to SCI is stopped
5
3
2
Rev. 4.0, 04/00, page 187 of 850
1
Advertisement
Table of Contents
