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10.2.2
CPG Pin Configuration
Table 10.1 shows the CPG pins and their functions.
Table 10.1 CPG Pins
Pin Name
Mode control pins
Crystal I/O pins
(clock input pins)
Clock output pin
CKIO enable pin
Note: * Set to 1 in a power-on reset.
10.2.3
CPG Register Configuration
Table 10.2 shows the CPG register configuration.
Table 10.2 CPG Register
Name
Frequency control
register
Note: * Depends on the clock operating mode set by pins MD2–MD0.
Abbreviation
MD0
MD1
MD2
XTAL
EXTAL
MD8
CKIO
CKE
Abbreviation
R/W
FRQCR
R/W
I/O
Function
Input
Set clock operating mode
Output
Connects crystal resonator
Input
Connects crystal resonator, or used as
external clock input pin
Input
Selects use/non-use of crystal resonator
When MD8 = 0, external clock is input from
EXTAL
When MD8 = 1, crystal resonator is
connected directly to EXTAL and XTAL
Output
Used as external clock output pin
Level can also be fixed
Output
0 when CKIO output clock is unstable*
Initial Value
P4 Address
Undefined*
H'FFC00000 H'1FC00000
Area 7
Address
Rev. 4.0, 04/00, page 201 of 850
Access
Size
16
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