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4.4
Instruction Cache (IC)
4.4.1
Configuration
Figure 4.5 shows the configuration of the instruction cache.
Effective address
31
26 25
IIX
22
MMU
19
Rev. 4.0, 04/00, page 72 of 850
[12]
8
Address array
Tag
0
255
19 bits
1 bit
Compare
Hit signal
Figure 4.5 Configuration of Instruction Cache
13 12 11 10 9
Longword (LW) selection
3
V
LW0
LW1
32 bits
32 bits
5 4 3 2 1
0
[11:5]
Data array
LW2
LW3
LW4
LW5
32 bits
32 bits
32 bits
32 bits
Read data
LW6
LW7
32 bits
32 bits
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