Page 1 Hard Disk Drive Specification Deskstar 7K80 3.5 inch Ultra ATA/133 hard disk drive Models: HDS728040PLAT20 HDS728080PLAT20 Version 1.6 12 September 2006...
Page 3 Hard Disk Drive Specification Deskstar 7K80 3.5 inch Ultra ATA/133 hard disk drive Models: HDS728040PLAT20 HDS728080PLAT20 Version 1.6 12 September 2006...
Page 4 It is possible that this publication may contain reference to, or information about, Hitachi products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Hitachi intends to announce such Hitachi products, programming, or services in your coun- try.
Page 5: Table Of Contents
Table Of Contents 1.0 General........................11 1.1 Introduction....................11 1.2 References....................11 1.3 Abbreviations...................11 1.4 Caution.....................13 2.0 General features of the drive ................15 3.0 Fixed-disk subsystem description..............19 3.1 Control electronics ...................19 3.2 Head disk assembly ................19 3.3 Actuator ....................19 4.0 Drive characteristics ..................21 4.1 Default logical drive parameters..............21 4.2 Data sheet....................22 4.3 World Wide Name Assignment ...............22...
Page 6 6.6.2 Read DRQ interval time ..............39 6.7 Multi-word DMA timings................41 6.8 Ultra DMA timings ..................42 6.8.1 Initiating Read DMA ..............42 6.8.2 Host Pausing Read DMA..............43 6.8.3 Host Terminating Read DMA............44 6.8.4 Device Terminating Read DMA.............45 6.8.5 Initiating Write DMA ..............46 6.8.6 Device Pausing Write DMA ............47 6.8.7 Device Terminating Write DMA ............48 6.8.8 Host Terminating Write DMA............49...
Page 7 7.7 Acoustics....................68 7.8 Identification labels..................68 7.9 Safety .......................69 7.9.1 UL and CSA approval..............69 7.9.2 German safety mark................69 7.9.3 Flammability ...................69 7.9.4 Safe handling ..................69 7.9.5 Environment..................69 7.9.6 Secondary circuit protection ............69 7.10 Electromagnetic compatibility ...............70 7.10.1 C-TICK mark ................70 7.10.2 BSMI mark ...................70 7.11 Packaging....................70 8.0 General........................71 8.1 Introduction....................71...
Page 8 10.5.3 Standby timer ................85 10.5.4 Interface capability for power modes ...........86 10.6 S.M.A.R.T. Function ................87 10.6.1 Attributes ..................87 10.6.2 Attribute values................87 10.6.3 Attribute thresholds...............87 10.6.4 Threshold exceeded condition ............87 10.6.5 S.M.A.R.T. commands ..............87 10.6.6 Off-line read scanning ..............87 10.6.7 Error log ..................88 10.6.8 Self-test ..................88 10.7 Security Mode Feature Set..............89 10.7.1 Security mode ................89...
Page 9 11.4 DMA commands..................113 12.0 Command descriptions..................115 12.1 Check Power Mode (E5h/98h) ..............120 12.2 Configure Stream (51h) .................121 12.3 Device Configuration Overlay (B1h) ............123 12.3.1 DEVICE CONFIGURATION RESTORE (Subcommand C0h).123 12.3.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)123 12.3.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h).124 12.3.4 DEVICE CONFIGURATION SET (subcommand C3h) .....124 12.4 Download Microcode (92h)..............127 12.5 Execute Device Diagnostic (90h) ............129...
Page 10 12.34 Security Set Password (F1h)..............189 12.35 Security Unlock (F2h) .................191 12.36 Seek (7xh) ...................193 12.37 Set Features (EFh) ................194 12.37.1 Set Transfer mode ...............195 12.37.2 Write Cache ................195 12.37.3 Advanced Power Management ...........195 12.37.4 Automatic Acoustic Management ..........197 12.38 Set Max ADDRESS (F9h) ..............198 12.38.1 Set Max Set Password (Feature=01h).........200 12.38.2 Set Max Lock (Feature=02h)............201 12.38.3 Set Max Unlock (Feature = 03h) ..........202...
Page 11 List of Tables Table 1.Formatted capacities ..................21 Table 2.Mechanical positioning performance ............22 Table 3.Word Wide Name Assignment ..............22 Table 4.Cylinder allocation..................23 Table 5.Command overhead ..................24 Table 6.Mechanical positioning performance ............24 Table 7.Full stroke seek time ..................25 Table 8.Head switch time ..................25 Table 9.Single track seek time ...................26 Table 10.Latency Time ....................26 Table 11.Drive ready time ..................26...
Page 12 Table 42.Temperature and humidity................58 Table 43.Limits of temperature and humidity ............59 Table 44.Input voltage ....................59 Table 45.Power supply current of 80GB and 40GB models ........60 Table 46.Power supply generated ripple at drive power connector......60 Table 47.Random vibration PSD ................65 Table 48.Random vibration PSD profile break points (operating) ......65 Table 49.Random Vibration PSD profile breakpoints (nonoperating) ......65 Table 50.Sinusoidal shock wave................67 Table 51.Rotational shock ..................67...
Page 13 Table 88.Identify device information (Part 4 of 7) ............139 Table 89.Identify device information (Part 5 of 7) ............140 Table 90.Identify device information (Part 6 of 7) ............141 Table 91.Identify device information (Part 7 of 7) ............142 Table 92.Idle command (E3h/97h) ................143 Table 93.Idle Immediate command (E1h/95h) ............144 Table 94.Initialize Device Parameters command (91h)..........145 Table 95.Read Buffer (E4h)..................146...
Page 14 Table 134.Set Max ADDRESS command (F9h) ............198 Table 135.Set Max Set Password command..............200 Table 136.Set Max Set Password data contents ............200 Table 137.Set Max Lock command ................201 Table 138.Set Max Unlock command (F9h) .............202 Table 139.Set Max Freeze Lock (F9h) ..............203 Table 140.Set Max Address Ext command (37h)............204 Table 141.Set Multiple command (C6h) ..............206 Table 142.Sleep command (E6h/99h) ...............207...
Page 15: General
1.0 General 1.1 Introduction This document describes the specifications of the Deskstar 7K80, a 3.5-inch hard disk drive with ATA interface and a rotational speed of 7200 RPM. HDS728040PLAT20 41.1GB HDS728080PLAT20 82.3GB For Serial ATA function specification, please refer to ’Serial ATA function - Addendum.’ These specifications are subject to change without notice.
Page 16 ground hexadecimal hard disk drive Hertz Input integrated lead suspension Input/Output International Standards Organization 1,000 bytes Kbpi 1000 bits per inch kgf-cm kilogram (force)-centimeter kilohertz logical block addressing unit of A-weighted sound power meter maximum 1,000,000 bytes Mbps 1,000,000 bits per second megahertz Machine Level Control millimeter...
Page 17: Caution
Underwriters Laboratory volt Verband Deutscher Electrotechniker watt 3-state transistor-transistor tristate logic 1.4 Caution • Do not apply force to the top cover. • Do not cover the breathing hole on the top cover. • Do not touch the interface connector pins or the surface of the printed circuit board •...
Page 18 Deskstar 7K80 Hard Disk Drive Specification...
Page 19: General Features Of The Drive
2.0 General features of the drive • Formatted capacities of 40 GB and 80 GB • Spindle speeds of 7200 RPM • Fluid Dynamic Bearing motor • Enhanced IDE interface • Sector format of 512 bytes/sector • Closed-loop actuator servo •...
Page 20 Deskstar 7K80 Hard Disk Drive Specification...
Page 21 Part 1. Functional specification Deskstar 7K80 Hard Disk Drive specification...
Page 22 Deskstar 7K80 Hard Disk Drive Specification...
Page 23: Fixed-Disk Subsystem Description
3.0 Fixed-disk subsystem description 3.1 Control electronics The drive is electronically controlled by a microprocessor, several logic modules, digital/analog modules, and var- ious drivers and receivers. The control electronics performs the following major functions: • Controls and interprets all interface signals between the host controller and the drive. •...
Page 24 Deskstar 7K80 Hard Disk Drive Specification...
Page 25: Drive Characteristics
4.0 Drive characteristics 4.1 Default logical drive parameters Table 1: Formatted capacities HDS728040PLAT20 HDS728080PLAT20 Physical Layout Label capacity (GB) Bytes per sector Sectors per track 567-1170 567-1170 Number of heads Number of disks Data sectors per cylinder 567-1170 1134-2340 Data cylinders per zone 1444-4501 1444-4501 Logical layout...
Page 26: Data Sheet
87 / 90 / 93 Areal density - max (Gbits/in Number of data bands 4.3 World Wide Name Assignment Table 3: Word Wide Name Assignment Description Organization Hitachi GST Hitachi GST Manufacturing Site Sriracha Plant, Thailand China Product Deskstar 7K80...
Page 27: Cylinder Allocation
This cylinder contains the user data which can be sent and retrieved via read/write commands and a spare area for reassigned data. Spare cylinder The spare cylinder is used by Hitachi Global Storage Technologies manufacturing and includes data sent from a defect location. Deskstar 7K80 Hard Disk Drive Specification...
Page 28: Performance Characteristics
4.5 Performance characteristics Drive performance is characterized by the following parameters: • Command overhead • Mechanical head positioning Seek time Latency • Data transfer speed • Buffering operation (Look ahead/Write cache) All the above parameters contribute to drive performance. There are other parameters that contribute to the perfor- mance of the actual system.
Page 29: Table 7.Full Stroke Seek Time
The terms “Typical” and “Max” are used throughout this document and are defined as follows: Typical The average of the drive population tested at nominal environmental and voltage conditions. Maximum value measured on any one drive over the full range of the environmental and voltage conditions.
Page 30: Drive Ready Time
4.5.2.4 Cylinder switch time (cylinder skew) Cylinder switch time - typical (ms) Cylinder switch time is defined as the amount of time required by the fixed disk to access the next sequential block after reading the last sector in the current cylinder. The measuring method is given in Section 4.5.5, “Throughput”...
Page 31: Data Transfer Speed
4.5.4 Data transfer speed Table 12: Data transfer speed Data transfer speed (Mbytes/sec) Disk-Buffer transfer (Zone 0) Instantaneous - typical Sustained - read typical 61.1 Disk-Buffer transfer (Zone 29) Instantaneous - typical 34.5 Sustained - read typical 29.6 Buffer - host (max) •...
Page 32: Throughput
4.5.5 Throughput 4.5.5.1 Simple sequential access The following table illustrates simple sequential access for the enclosure. Table 13: Simple Sequential Access performance Operation Typical (sec) Max (sec) Sequential Read (Zone 0) 0.32 Sequential Read (Zone 29) 0.61 0.63 The above table gives the time required to read a total of 8000h consecutive blocks (16,777,216 bytes) accessed by 128 read commands.
Page 33: Operating Modes
D = Average sustained disk-buffer transfer rate (byte/s) E = Buffer-host transfer rate (byte/s) 4.5.6 Operating modes 4.5.6.1 Description of operating modes Table 15: Description of operating modes Operating mode Description Start up time period from spindle stop or power down. Spin-up Seek operation mode Seek...
Page 34 Deskstar 7K80 Hard Disk Drive Specification...
Page 35: Defect Flagging Strategy
5.0 Defect flagging strategy Media defects are remapped to the next available sector during the Format Process in manufacturing. The mapping from LBA to the physical locations is calculated by an internally maintained table. Shipped format • Data areas are optimally used. •...
Page 36 Deskstar 7K80 Hard Disk Drive Specification...
Page 37: Electrical Interface Specification
6.0 Electrical interface specification 6.1 Connector location Refer to the following illustration to see the location of the connectors Figure 1 : Connector location 6.1.1 DC power connector The DC power connector is designed to mate with AMP part number 1-480424-0 using AMP pins part number 350078-4 (strip), part number 61173-4 (loose piece), or their equivalents.
Page 38: Signal Definitions
6.2 Signal definitions The pin assignments of interface signals are listed as follows: Table 18: Signal definitions SIGNAL Type SIGNAL Type RESET- 3–state DD08 3–state 3–state DD09 3–state 3–state DD10 3–state 3–state DD11 3–state 3–state DD12 3–state 3–state DD13 3–state 3–state DD14 3–state...
Page 39: Signal Descriptions
6.3 Signal descriptions Table 19: Special signal definitions for Ultra DMA Special Definition Conventional (for Ultra DMA) Definition DDMARDY- IORDY Write Operation HSTROBE DIOR- STOP DIOW- HDMARDY- DIOR- Read Operation DSTROBE IORDY STOP DIOW- DD00–DD15 A 16-bit bi-directional data bus between the host and the drive. The lower 8 lines, DD00-07, are used for Regis- ter and ECC access.
Page 40 DASP- This is a time-multiplexed signal which indicates that a drive is active or that device 1 is present. This signal is driven by an Open-Drain driver and internally pulled up to 5 volts through a 10 kW resistor. During a Power-On initialization or after RESET- is negated, DASP- shall be asserted by Device 1 within 400 ms to indicate that device 1 is present.
Page 41 DMACK- This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted, or that data is available. This signal is internally pulled up to 5 Volt through a 15kΩ resistor with a resistor tolerance value of –50% to +100%.
Page 42: Interface Logic Signal Levels
6.4 Interface logic signal levels The interface logic signals have the following electrical specifications: Input High Voltage 2.0 V min Inputs Input Low Voltage 0.8 V max. Output High Voltage 2.4 V min. Outputs: Output Low Voltage 0.5 V max. 6.5 Reset timings Table 20: System reset timing chart RESET-...
Page 43: Pio Timings
6.6 PIO timings The PIO cycle timings meet Mode 4 of the ATA/ATAPI-6 description. Table 22: PIO cycle timings chart PARAMETER DESCRIPTION MIN (ns) MAX (ns) Cycle time – Address valid to DIOR-/DIOW- setup – DIOR-/DIOW- pulse width – DIOR-/DIOW- recovery time –...
Page 44 • In the event that a host reads the status register only before the sector or block transfer DRQ interval, the DRQ interval 4.2 µs • In the event that a host reads the status register after or both before and after the sector or block transfer, the DRQ interval is 11.5 µs Deskstar 7K80 Hard Disk Drive Specification...
Page 45: Multi-Word Dma Timings
6.7 Multi-word DMA timings The Multiword DMA timings meet Mode 2 of the ATA/ATAPI-6 description. Table 23: Multiword DMA cycle timing chart CS0-/CS1- tLR/tLW DMARQ DMACK- tKR/tKW DIOR-/DIOW- READ DATA WRITE DATA Table 24: Multiword DMA cycle timings PARAMETER DESCRIPTION MIN (ns) MAX (ns) –...
Page 46: Ultra Dma Timings
6.8 Ultra DMA timings The Ultra DMA timings meet Mode 0, 1, 2, and 4, 5 and 6 of the Ultra DMA Protocol. 6.8.1 Initiating Read DMA DMARQ DMACK- tACK tENV STOP tACK tENV t2CYC HDMARDY- tZIORDY tCYC tCYC DSTROBE tZAD DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxx...
Page 47: Host Pausing Read Dma
6.8.2 Host Pausing Read DMA Table 26: Ultra DMA cycle timing chart (Host pausing Read) DMARQ DMACK- STOP HDMARDY- tRFS DSTROBE Table 27: Ultra DMA cycle timings (Host pausing Read) PARAMETER MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 DESCRIPTION...
Page 48: Host Terminating Read Dma
6.8.3 Host Terminating Read DMA Table 28: Ultra DMA cycle timing chart (Host pausing Read) DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tRFS tIORDYZ DSTROBE xxxxxxxxxxxxxxxxxx RD Data xxxxxxxxxxx DD(15:0) tZAH Device drives DD Host drives DD Table 29: Ultra DMA cycle timings (Host pausing Read) PARAMETER DESCRIP- MODE 0 MODE 1...
Page 49: Device Terminating Read Dma
6.8.4 Device Terminating Read DMA Table 30: Ultra DMA cycle timing chart (Host pausing Read) DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tIORDYZ DSTROBE xxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) tZAH Host drives DD Device drives DD Table 31: Ultra DMA cycle timings (Device Terminating Read) PARAMETER DESCRIP- MODE 0 MODE 1...
Page 50: Initiating Write Dma
6.8.5 Initiating Write DMA Table 32: Ultra DMA cycle timing chart (Initiating Write) DMARQ DMACK- tENV tACK STOP tZIORDY t2CYC DDMARDY- tCYC tCYC tACK HSTROBE DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx WT Data WT Data WT Data Host drives DD PARAMETER MODE 0 MODE 1 MODE 2 MODE 3 MODE 4...
Page 51: Device Pausing Write Dma
6.8.6 Device Pausing Write DMA Table 33: Ultra DMA cycle timing chart (Device Pausing Write) DMARQ DMACK- STOP DDMARDY- tRFS HSTROBE Table 34: Ultra DMA cycle timings (Device Pausing Write) PARAMETER MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 DESCRIPTION...
Page 52: Device Terminating Write Dma
6.8.7 Device Terminating Write DMA Table 35: Ultra DMA cycle timing chart (Device Terminating Write) DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK tRFS HSTROBE xxx WT Data xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD PARAMETER MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5...
Page 53: Host Terminating Write Dma
6.8.8 Host Terminating Write DMA Table 37: Ultra DMA cycle timing chart (Host Terminating Write) DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK HSTROBE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD Table 38: Ultra DMA cycle timings (Host Terminating Write) PARAMETER MODE 0 MODE 1 MODE 2...
Page 54: Addressing Of Registers
6.9 Addressing of registers The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's I/O space. Two chip select lines (CS0– and CS1–) and three address lines (DA0–2) are used to select one of these registers, while a DIOR–...
Page 55 Part 2. Interface specification Deskstar 7K80 Hard Disk Drive Specification...
Page 56 Deskstar 7K80 Hard Disk Drive Specification...
Page 57: Specification
7.0 Specification 7.1 Jumper settings 7.1.1 Jumper pin location Jumper pins Jumper pins 7.1.2 Jumper pin identification Pin I Pin A DERA001.prz Pin B Deskstar 7K80 Hard Disk Drive Specification...
Page 58: Jumper Pin Assignment
7.1.3 Jumper pin assignment There are four jumper settings as shown in the following sections: • 16 logical head default (normal use) • 15 logical head default • 32 GB clip • Power up in standby Within each of these four jumper settings the pin assignment selects Device 0, Device 1, Cable Selection, or Device 1 Slave Present as shown in the following figures.
Page 59 Notes: 1. To enable the CSEL mode (Cable Selection mode) the jumper block must be installed at E-F. In the CSEL mode the drive address is determined by AT interface signal #28 CSEL as follows: • When CSEL is grounded or at a low level, the drive address is 0 (Device 0). •...
Page 60: Table 40.Jumper Positions For Capacity Clip To 32Gb
7.1.4.3 Capacity clip to 32GB The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device1 (Slave) Present while setting the drive capacity down to 32 GB for the purpose of compatibility. Table 40: Jumper positions for capacity clip to 32GB DEVICE 0 (M aster) DEVICE 1...
Page 61 Notes: 1. These jumper settings are used for limiting power supply current when multiple drives are used. 2. Command to spin up is SET FEATURES (subcommand 07h). Refer to 12.28 Set Features. 3. To enable the CSEL mode (Cable Selection mode) the jumper block must be installed at E-F. In the CSEL mode the drive address is determined by AT interface signal #28 CSEL as follows: •...
Page 62: Environment
7.2 Environment 7.2.1 Temperature and humidity Table 42: Temperature and humidity Operating conditions Temperature 5C to 55ºC (See note below) Relative humidity 8 to 90%, non-condensing Maximum wet bulb temperature 29.4ºC, non-condensing Maximum temperature gradient 15ºC/hour Altitude –300 to 3,048 m Non-operating conditions Temperature –40C to 65ºC...
Page 63: Corrosion Test
Table 43: Limits of temperature and humidity 1 0 0 3 6 ' C / 9 5 % W e t B u i b = 3 5 . 0 ' C 3 1 ' C / 9 0 % W e t B u i b = 2 9 .
Page 64: Power Supply Current (Typical)
7.3.2 Power supply current (typical) Table 45: Power supply current of 80GB and 40GB models Power supply current of 40 GB +5 Volts [mA] +12 Volts [mA] Total and 80 GB models(PATA) (values in milliamps. RMS) Pop Mean Std Dev Pop Mean Std Dev Idle average...
Page 65: Reliability
7.4 Reliability 7.4.1 Data integrity No more than one sector is lost at Power loss condition during the write operation when the write cache option is disabled. If the write cache option is active, the data in write cache will be lost. To prevent the loss of customer data, it is recommended that the last write access before power off be issued after setting the write cache off.
Page 66: Mechanical Specifications
7.5 Mechanical specifications 7.5.1 Physical dimensions and weight BREATHER HOLE All dimensions in the above figure are in millimeters. The breather hole must be kept uncovered in order to keep the air pressure inside of the disk enclosure equal to external air pressure.
Page 67: Mounting Hole Locations
7.5.2 Mounting hole locations The mounting hole locations and size of the drive are shown below. All dimensions are in mm. (6X) Max. penetration 4.5 mm Side View I/F Connector Bottom View (4X) Max. penetration 4.0 mm Thread 6-32 UNC 41.28±0.5 44.45±0.2 95.25±0.2...
Page 68: Drive Mounting
7.5.4 Drive mounting The drive will operate in all axes (6 directions). Performance and error rate will stay within specification limits if the drive is operated in the other orientations from which it was formatted. For reliable operation, the drive must be mounted in the system securely enough to prevent excessive motion or vibration of the drive during seek operation or spindle rotation, using appropriate screws or equivalent mounting hardware.
Page 69: Vibration And Shock
7.6 Vibration and shock All vibration and shock measurements recorded in this section are made with a drive that has no mounting attach- ments for the systems. The input power for the measurements is applied to the normal drive mounting points. 7.6.1 Operating vibration 7.6.1.1 Random vibration The test is 30 minutes of random vibration using the power spectral density (PSD) levels shown below in each of...
Page 70: Operating Shock
The overall RMS (root mean square) level of vibration is 1.04 G. 7.6.2.2 Swept sine vibration • 2 G (zero-to-peak), 5 to 500 to 5 Hz sine wave • 0.5 oct/min sweep rate • 3 minutes dwell at two major resonances 7.6.3 Operating shock The drive meets the following criteria while operating in the conditions described below.
Page 71: Nonoperating Rotational Shock
7.6.4.2 Sinusoidal shock wave The shape is approximately half-sine pulse. The figure below shows the maximum acceleration level and duration. Table 51: Sinusoidal shock wave Acceleration level (G) Duration (ms) 7.6.5 Nonoperating rotational shock All shock inputs shall be applied around the actuator pivot axis. Table 52: Rotational shock Duration Rad/s...
Page 72: Acoustics
7.8 Identification labels The following labels are affixed to every drive: • A label containing the Hitachi logo, the Hitachi Global Storage Technologies part number and the statement " Made by Hitachi Global Storage Technologies Inc." or Hitachi Global Storage Technol- ogies approved equivalent.
Page 73: Safety
United Nations Environment Program Montreal Protocol, and as ratified by the member nations. Material to be controlled include CFC-11, CFC-12, CFC-113, CFC-114, CFC-115, Halon 1211, Halon 1301 and Halon 2402. Although not specified by the Protocol, CFC-112 is also controlled. In addition to the Protocol Hitachi Global Stor- age Technologies requires the following: •...
Page 74: Electromagnetic Compatibility
The product is declared to be in conformity with requirements of the following EC directives under the sole responsibility of Hitachi Global Storage Technologies Japan Ltd: Council Directive 89/336/EEC on the approximation of laws of the Member States relating to electromagnetic compatibility.
Page 75: General
8.0 General 8.1 Introduction This specification describes the host interface of the HDS7280x0PLATy0 hard disk drive. The interface conforms to the Working Document of Information technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-7) Revision 4, dated 23 December 2003, with certain limitations described in Section 8.3 below.
Page 76 Deskstar 7K80 Hard Disk Drive Specification...
Page 77: Registers
9.0 Registers 9.1 Register set Table 54: Register Set Addresses Functions CS0- CS1- READ (DIOR-) WRITE (DIOW-) Data bus high impedance Not used Control block registers Data bus high impedance Not used Data bus high impedance Not used Alternate Status Device Control Device Address Not used...
Page 78: Alternate Status Register
9.2 Alternate Status Register Table 55: Alternate Status Register DSC/ SERV This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt.
Page 79: Data Register
9.6 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and the configuration information is transferred on an Identify Device command.
Page 80: Drive Address Register
9.8 Drive Address Register Table 57: Drive Address Register -WTG -DS1 -DS0 This register contains the inverted drive select and head select addresses of the currently selected drive. Definitions High Impedance. This bit is not a device and will always be in a high impedance state. -WTG Write Gate.
Page 81: Error Register
9.10 Error Register Table 59: Error Register IDNF ABRT TK0NF AMNF This register contains the status from the last command executed by the device or a diagnostic code. At the comple- tion of any command, except Execute Device Diagnostic, the contents of this register are always valid even if ERR = 0 is in the Status Register.
Page 82: Sector Number Register
9.13 Sector Number Register This register contains the starting sector number for any disk data access for the subsequent command. The sector number is from one to the maximum number of sectors per track. In LBA mode, this register contains Bits 0–7. At the end of the command this register is updated to reflect the cur- rent LBA Bits 0–7.
Page 83 Definitions Busy. Bit BSY=1 whenever the device is accessing the registers. The host should not read or write any registers when BSY=1. If the host reads any register when BSY=1, the contents of the Status Register will be returned. DRDY Device Ready.
Page 84 Deskstar 7K80 Hard Disk Drive Specification...
Page 85: General Operation
10.0 General operation 10.1 Reset response ATA has the following three types of resets: The device executes a series of electrical circuitry diagnostics, spins up the Power On Reset (POR) head disk assembly, tests speed and other mechanical parametric, and sets default values.
Page 86: Register Initialization
10.2 Register initialization After a power on, a hard reset, or a software reset, the register values are initialized as shown in the table below. Table 62: Default Register Values Register Default Value Error Diagnostic Code Sector Count Sector Number Cylinder Low Cylinder High Device/Head...
Page 87: Diagnostic And Reset Considerations
10.3 Diagnostic and Reset considerations For each Reset and Execute Device Diagnostic, the diagnostic is done as follows: Power On Reset DASP– is read by Device 0 to determine if Device 1 is present. If Device 1 is present, Device 0 shall read PDIAG– to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error, otherwise Device 0 clears the BSY bit whenever it is ready to accept commands.
Page 88: Sector Addressing Mode
10.4 Sector Addressing Mode All addressing of data sectors recorded on the device's media is done by a logical sector address. The logical CHS address for HDS7280x0PLATy0 is different from the actual physical CHS location of the data sector on the disk media.
Page 89: Power Management Features
10.5 Power management features The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.
Page 90: Interface Capability For Power Modes
10.5.4 Interface capability for power modes Each power mode affects the physical interface as defined in the following table: Table 65: Power conditions Mode Interface active Media Active Active Idle Active Standby Inactive Sleep Inactive Ready (RDY) is not a power condition. A device may post ready at the interface even though the media may not be accessible.
Page 91: Function
10.6 S.M.A.R.T. Function The intent of Self-monitoring, analysis, and reporting technology (S.M.A.R.T.) is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, S.M.A.R.T. devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault condition.
Page 92: Error Log
10.6.7 Error log Logging of reported errors is supported. The device provides information on the last five errors that the device reported as described in the SMART error log sector. The device may also provide additional vendor specific information on these reported errors. The error log is not disabled when SMART is disabled. Disabling SMART disables the delivering of error log information via the SMART READ LOG SECTOR command.
Page 93: Security Mode Feature Set
10.7 Security Mode Feature Set Security Mode Feature Set is a powerful security feature. With a device lock password, a user can prevent unauthorized access to a device even if it is removed from the computer. New commands are supported for this feature as listed below: Security Set Password ('F1'h) Security Unlock...
Page 94: Passwords
10.7.3 Passwords This function can have two types of passwords as described below. Master Password When the Master Password is set, the device does NOT enable the Device Lock Function, and the device CANNOT be locked with the Master Password, but the Master Password can be used for unlocking the locked device.
Page 95: Table 65.Initial Setting
10.7.4.2 User Password setting When a User Password is set, the device will automatically enter lock mode the next time the device is powered on. < Setting password > < No setting password > Set Password with User Password Normal operation Normal operation Power off Power off...
Page 96: Table 66.Usual Operation For Por
is successfully completed. Device Locked mode Unlock CMD Erase Prepare Media Access Non-media Access Command (*1) Command (*1) Erase Unit Password Password Match ? Match ? Reject Complete Enter Device Complete Unlock mode Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode...
Page 97: Table 67.Password Lost
10.7.4.4 User Password lost If the User Password is forgotten and High level security is set, the system user cannot access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.
Page 98: Command Table
10.7.5 Command table This table shows the device's response to commands when the Security Mode Feature Set (Device lock function) is enabled. Command Locked Mode Unlocked Mode Frozen Mode Check Power Mode Executable Executable Executable Configure Stream Command aborted Executable Executable Execute Device Executable...
Page 99 Security Erase Prepare Executable Executable Command aborted Security Erase Unit Executable Executable Command aborted Security Freeze Lock Command aborted Executable Executable Security Set Password Command aborted Executable Command aborted Security Unlock Executable Executable Command aborted Seek Executable Executable Executable Set Features Executable Executable Executable...
Page 100: Host Protected Area Feature
10.8 Host Protected Area Feature Host Protected Area Feature provides a protected area which cannot be accessed via conventional methods. This protected area is used to contain critical system data such as BIOS or system management information. The contents of the main memory of the entire system may also be dumped into the protected area to resume after a system power off.
Page 101: Security Extensions
3. Conventional usage without system software support Since the drive works as a 6.2 GB device, there is no special care required for normal use of this device. 4. Advanced usage using protected area The data in the protected area is accessed by the following steps. i.
Page 102: Seek Overlap
10.9 Seek overlap HDS7280x0PLATy0 provides an accurate method for measuring seek time. The seek command is usually used to measure the device seek time by accumulating the execution time for a number of seek commands. With typical implementation of seek command this measurement must include the device and host command overhead. To eliminate this overhead the drive overlaps the seek command as described below.
Page 103: Write Cache Function
10.10 Write cache function Write cache is a performance enhancement whereby the device reports the completion of the write command (Write Sectors, Write Multiple, and Write DMA) to the host as soon as the device has received all of the data into its buffer. The device assumes the responsibility for subsequently writing the data onto the disk.
Page 104: Reassign Function
10.11 Reassign function The Reassign function is used with read commands and write commands. The sectors of data for reassignment are prepared as the spare data sector. This reassignment information is registered internally and the information is available right after completing the Reassign function.
Page 105: Power-Up In Standby Feature Set
10.12 Power-Up in Standby feature set The Power-Up In Standby feature set allows devices to be powered-up into the Standby power management state to minimize inrush current at power-up and to allow the host to sequence the spin-up of devices. This feature set will be enabled and disabled via the SET FEATURES command or the use of a jumper.
Page 106: Advanced Power Management Feature Set (Apm)
10.13 Advanced Power Management feature set (APM) This feature allows the host to select an advanced power management level. The advanced power management level is a scale from the lowest power consumption setting of 01h to the maximum performance level of FEh. Device performance may increase with increasing advanced power management levels.
Page 107: Automatic Acoustic Management Feature Set (Aam)
10.14 Automatic Acoustic Management feature set (AAM) This feature set allows the host to select an acoustic management level. The acoustic management level may range from the lowest acoustic emanation setting of 01h to the maximum performance level of FEh. Device performance and acoustic emanation may increase with increasing acoustic management levels.
Page 108: Address Offset Feature
10.15 Address Offset Feature Computer systems perform initial code loading (booting) by reading from a predefined address on a drive. To allow an alternate bootable operating system to exist in a system reserved area on a drive, this feature provides a Set Features function to temporarily offset the drive address space.
Page 109: Identify Device Data
10.15.2 Identify Device Data Identify Device data, word 83, bit 7 indicates the device supports the Address Offset Feature. Identify Device data, word 86, bit 7 indicates the device is in Address Offset mode. 10.15.3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error, even if the access protection is removed by a Set Max Address command.
Page 110: 48-Bit Address Feature Set
10.16 48-bit Address Feature Set The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This allows device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that may be transferred by a single command are increased by increasing the allowable sector count to 16 bits. Commands unique to the 48-bit Address feature set are •...
Page 111: Streaming Commands
• Read Stream DMA • Write Stream DMA • Read Log Ext Support of the Streaming feature set is indicated in Identify Device work 84 bit 4. Note that PIO versions of these commands limit the transfer rate (16.6 MB/s), provide no CRC protection, and limit status reporting as compared to a DMA implementation.
Page 112: Not Sequential Bit
10.17.4 Not Sequential bit The Not Sequential bit specifies that the next read stream command with the same Stream ID may not be sequential in LBA space. This information helps the device with pre-fetching decisions. 10.17.5 Read Continuous bit If the Read Continuous bit is set to one for the command, the device shall transfer the requested amount of data to the host within the Command Completion Time Limit even if an error occurs.
Page 113: Command Protocol
11.0 Command protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check to see if BSY = 1, and should proceed no further unless and until BSY = 0.
Page 114: Pio Data Out Commands
e. The host reads one sector (or block) of data via the Data Register. f. The device sets DRQ = 0 after the sector (or block) has been transferred to the host. 4. For the Read Long command: a. The device sets BSY = 1 and prepares for data transfer. b.
Page 115 • Write Multiple Ext • Write Sector(s) • Write Sector(s) Ext Execution includes the transfer of one or more 512 byte (> 512 bytes on Write Long) sectors of data from the host to the device. 1. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head Registers.
Page 116: Non-Data Commands
11.3 Non-data commands The following are Non-data commands: • Check Power Mode • Device Configuration FREEZE LOCK • Device Configuration RESTORE • Execute Device Diagnostic • Flush Cache • Flush Cache Ext • Idle • Idle Immediate • Initialize Device Parameters •...
Page 117: Dma Commands
11.4 DMA commands The following are DMA commands: • Read DMA • Read DMA Ext • Read Stream DMA • Write DMA • Write DMA Ext • Write Stream DMA Data transfers using DMA commands differ in two ways from PIO transfers: •...
Page 118 Deskstar 7K80 Hard Disk Drive Specification...
Page 119: Command Descriptions
12.0 Command descriptions The table below shows the commands that are supported by the device. Table 72: “Command Set (subcommand)” on page 118 shows the subcommands that are supported by each command or feature. Table 71: Command Set 6 5 4 3 2 1 0 Protocol (Hex) Command...
Page 120 6 5 4 3 2 1 0 Protocol Command (Hex) Read Sector(s) 0 0 1 Read Sector(s) 0 0 1 Read Sector(s) Ext 0 0 1 Read Stream DMA 0 0 1 Read Stream PIO 0 0 1 Read Verify Sector(s) 0 1 0 Read Verify Sector(s) 0 1 0...
Page 121 6 5 4 3 2 1 0 Protocol (Hex) Command Standby 1 1 1 Standby* 1 0 0 Standby Immediate 1 1 1 Standby Immediate* 1 0 0 Write Buffer 1 1 1 Write DMA 1 1 0 Write DMA 1 1 0 Write DMA Ext 0 0 1...
Page 122: Table 71.Command Set (Subcommand)
Commands marked * are alternate command codes for previously defined commands Protocol: 1 : PIO data IN command 2 : PIO data OUT command 3 : Non data command 4 : DMA command + : Vendor specific command Table 72: Command Set (subcommand) Command Feature Command (Subcommand)
Page 123 The following symbols are used in the command descriptions. Output registers This indicates that the bit must be set to 0. This indicates that the bit must be set to 1. The device number bit. Indicates that the device number bit of the Device/Head Register should be specified.
Page 124: Check Power Mode (E5H/98H)
12.1 Check Power Mode (E5h/98h) Table 73: Check Power Mode command (E5h/98h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 125: Configure Stream (51H)
12.2 Configure Stream (51h) Table 74: Configure Stream (51h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 126 Feature Current bit 7 (A/R) If set to one, a request to add a new stream. If cleared to zero, a request to remove a previous configured stream is specified. Feature Previous The default Command Completion Time Limit (CCTL). The value is calculated as follows: (Default CCTL) = ((content of the Features register)* (Identify Device words (99:98))) micriseconds.
Page 127: Device Configuration Overlay (B1H)
12.3 Device Configuration Overlay (B1h) Table 75: Check Power Mode Command (E5h/98h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 128: Device Configuration Identify (Subcommand C2H).124
12.3.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h) The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure via PIO data-in transfer. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities, the response to an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command will reflect the reduced set of capabilities, while the DEVICE CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities.
Page 129: Table 76.Device Configuration Overlay Data Structure
Table 77: Device Configuration Overlay Data structure Word Content 0001h Data Structure revision Multiword DMA modes supported 15-3 Reserved 1 = Multiword DMA mode 2 and below are supported 1 = Multiword DMA mode 1 and below are supported 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported 15-6 Reserved...
Page 130: Table 77.Dco Error Information Definition
Table 78: DCO error information definition Word Content 0001h Data Structure revision Multiword DMA modes supported 15-3 Reserved 1 = Multiword DMA mode 2 and below are supported 1 = Multiword DMA mode 1 and below are supported 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported 15-7 Reserved...
Page 131: Download Microcode (92H)
12.4 Download Microcode (92h) Table 79: Downlad Microcode Command (92h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 132 device does not recognize the slave device even though it exists. Also when the spin-up of the device is disabled, the device spins down after reloading new microcode. Deskstar 7K80 Hard Disk Drive Specification...
Page 133: Execute Device Diagnostic (90H)
12.5 Execute Device Diagnostic (90h) Table 80: Execute Device Diagnostic command (90h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 134: Flush Cache (E7H)
12.6 Flush Cache (E7h) Table 81: Flush Cache command (E7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 135: Flush Cache Ext (Eah)
12.7 Flush Cache Ext (EAh) Table 82: Flush Cache Ext Command (EAh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 136: Format Track (50H)
12.8 Format Track (50h) Table 83: Format Track command (50h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 137 Input parameters from the device Sector Number In LBA mode this register specifies the current LBA address bits as 0–7 (L = 1). Cylinder High/Low In LBA mode this register specifies the current LBA address bits as 8–15 (Low) and bits 16–23 (High).
Page 138: Format Unit (F7H)
12.9 Format Unit (F7h) Table 84: Format Unit command (F7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 139: Identify Device (Ech)
12.10 Identify Device (ECh) Table 85: Identify Device command (ECh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 140: Table 85.Identify Device Information (Part 1 Of 7)
Table 86: Identify device information (Part 1 of 7) Word Content Description 045AH Drive classification, bit assignments: 15 (=0): 1=ATAPI device, 0=ATA device 045EH 14 - 8 : retired 7 (=0): 1=removable cartridge device 6 (=1): 1=fixed device 5 - 3 : retired 2 (=0): Response incomplete...
Page 141: Table 86.Identify Device Information (Part 2 Of 7)
Table 87: Identify device information (Part 2 of 7) Description Word Content Capabilities, bit assignments: xF00H 15-14 (=0) Reserved Standby timer (=1) values as specified in ATA standard are supported (=0) values are vendor specific 12 (=0) Reserved 11 (=1) IORDY Supported 10 (=1) IORDY can be disabled...
Page 142: Table 87.Identify Device Information (Part 3 Of 7)
Table 88: Identify device information (Part 3 of 7) Word Content Description 0078H Manufacturer's Recommended Multiword DMA Transfer Cycle Time 15-0(=78) Cycle time in nanoseconds (120ns, 16.6MB/s) 00F0H Minimum PIO Transfer Cycle Time Without Flow Control 15-0(=F0) Cycle time in nanoseconds (240ns, 8.3MB/s) 0078H Minimum PIO Transfer Cycle Time With IORDY Flow Control 15- 0(=78)
Page 143: Table 88.Identify Device Information (Part 4 Of 7)
Table 89: Identify device information (Part 4 of 7) Word Content Description 7FEBH Command set supported 15-14(=01) Word 83 is valid 13 (=1) FLUSH CACHE EXT command supported 12 (=1) FLUSH CACHE command supported 11 (=1) Device Configuration Overlay command supported 10 (=1) 48-bit Address feature set supported 9 (=1)
Page 144: Table 89.Identify Device Information (Part 5 Of 7)
Table 90: Identify device information (Part 5 of 7) Word Content Description xxxxH Command set/feature enabled 15-14 Reserved FLUSH CACHE EXT command supported FLUSH CACHE command supported Device Configuration Overlay command enabled 48-bit Address features set supported Automatic Acoustic Management enabled Set Max Security extensions enabled Set Features Address Offset mode Set Features subcommand required to spin-up...
Page 145: Table 90.Identify Device Information (Part 6 Of 7)
Table 91: Identify device information (Part 6 of 7) Word Content Description 0x7FH Ultra DMA Transfer modes 15- 8(=xx) Current active Ultra DMA transfer mode Reserved (=0) Mode 6 1 = Active 0 = Not Active Mode 5 1 = Active 0 = Not Active Mode 4 1 = Active...
Page 146: Table 91.Identify Device Information (Part 7 Of 7)
Table 92: Identify device information (Part 7 of 7) An asterisk (*) in next to the Content field indicates the use of those parameters that are vendor specific Word Content Description xxxxH Current Automatic Acoustic Management value 15-8 Vendor's Recommended Acoustic Management level 7-0 Current Automatic Acoustic Management value Stream Minimum Request Size Number of sectors that provides optimum performance in streaming environment.
Page 147: Idle (E3H/97H)
12.11 Idle (E3h/97h) Table 93: Idle command (E3h/97h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 148: Idle Immediate (E1H/95H)
12.12 Idle Immediate (E1h/95h) Table 94: Idle Immediate command (E1h/95h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 149: Initialize Device Parameters (91H)
12.13 Initialize Device Parameters (91h) Table 95: Initialize Device Parameters command (91h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 150: Read Buffer (E4H)
12.14 Read Buffer (E4h) Table 96: Read Buffer (E4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 151: Read Dma (C8H/C9H)
12.15 Read DMA (C8h/C9h) Table 97: Read DMA command (C8h/C9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 152 Sector Number This indicates the sector number of the last transferred sector. (L = 0). In LBA mode this register contains the current LBA bits 0–7. (L = 1) Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0). In LBA mode this register contains the current LBA bits 8–15 (Low) and bits16–23 (High).
Page 153: Read Dma Ext (25H)
12.16 Read DMA Ext (25h) Table 98: Read DMA Ext Command (25h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 154 Cylinder High Current LBA (23:16) Cylinder High Previous LBA (47:40) Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24)of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8)of the address of the first unrecoverable error.
Page 155: Read Log Ext (2Fh)
12.17 Read Log Ext (2Fh) Table 99: Read Log Ext Command (2Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 156: Table 99.Log Address Definition
Table 100: Log Address Definition Log Address Content Feature set Type Log directory Read Only Extended Comprehensive SMART error log SMART error logging Ready Only SMART self-test log SMART self-test See Note Extended SMART self-test log SMART self-test Read Only Streaming Performance log Streaming Read Only...
Page 157: General Purpose Log Directory
12.17.1 General Purpose Log Directory The figure below defines the 512 bytes that make up the General Purpose Log Directory. Table 101: General Purpose Log Directory Description Bytes Offset General purpose logging version Number of sectors in the log at log address 01h (7:0) Number of sectors in the log at log address 01h (15:8) Number of sectors in the log at log address 01h (7:0) Number of sectors in the log at log address 01h (15:8)
Page 158: Extended Comprehensive Smart Error Log
12.17.2 Extended Comprehensive SMART Error Log The figure below defines the format of each of the sectors that comprise the Extended Comprehensive SMART error log. Error log data structure shall not include errors attributed to the receipt of faulty commands such as com- mand codes not implemented by the device or requests with invalid parameters or in valid addresses.
Page 159: Table 103.Command Data Structure
12.17.2.3.2 Data format of command data structure Table 104: Command data structure Description Bytes Offset Device Control register Features register (7:0) (see Note) Features register (15:8) Sector count register(7:0) Sector count register(15:8) Sector number register(7:0) Sector number register(15:8) Cylinder Low register (7:0) Cylinder Low register (15:8) Cylinder High register (7:0) Cylinder High register (15:8)
Page 160: Extended Self-Test Log Sector
Note: bits (7:0) refer to the contents if the register is read with bit 7 of the Device Control register cleared to zero. Bits (15:8) refer to the contents if the register is read with bit 7 of the Device Control register set to one. State shall contain a value indicating the state of the device when the command was issued to the device or the reset occurred as described below.
Page 161: Read Stream Error Log
12.17.3.1 Self-test log data structure revision number The value of this revision number shall be 01h. 12.17.3.2 Self-test descriptor index This indicates the most recent self-test descriptor. If there have been no self-tests, this is set to zero. Valid values for the Self-test descriptor index are 0 to 18.
Page 162: Write Stream Error Log
Table 106: Read Stream Error Log The Data Structure Version field shall contain a value of 02h indicating the second revision of the structure format. The Read Stream Error Log Count field shall contain the number of uncorrected sector entries currently reportable to the host.
Page 163: Streaming Performance Log
successful completion of the Read Log Ext command with LBA Low register set to 21h. This error count may be greater than 31, but only the most 31 errors are represented by entries in the log. If the Write Stream Error Count reaches the maximum value that can be represented after the next error is detected the Write Stream Error Count shall remain at the maximum value.
Page 164: Table 108.Streaming Performance Parameters Log
The host should base its calculations on the larger of its Typical Host Interface Sector Time and the device reported Sector Time values, and on the sum of the device reported Access Time values and any additional latency that only the host is aware of (e.g.
Page 165: Read Long (22H/23H)
12.18 Read Long (22h/23h) Table 112: Read Long (22h/23h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 166 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred Sector Number This indicates the sector number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 0–7. (L = 1) Cylinder High/Low This indicates the cylinder number of the transferred sector.
Page 167: Read Multiple (C4H)
12.19 Read Multiple (C4h) Table 113: Read Multiple (C4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 168: Read Multiple Ext (29H)
12.20 Read Multiple Ext (29h) Table 114: Read DMA Ext Command (25h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 169 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 170: Read Native Max Address (F8H)
12.21 Read Native Max ADDRESS (F8h) Table 115: Read Native Max ADDRESS (F8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...
Page 171: Read Native Max Address Ext (27H)
12.22 Read Native Max Address Ext (27h) Table 116: Read Native Max Address Ext command (27h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
Page 172: Read Sectors (20H/21H)
12.23 Read Sectors (20h/21h) Table 117: Read Sectors Command (20h/21h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 173 Cylinder High/Low This is the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This is the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.
Page 174: Read Sector(S) Ext (24H)
12.24 Read Sector(s) Ext (24h) Table 118: Read Sector(s) Ext command (24h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 175 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 176: Read Stream Dma (2Ah)
12.25 Read Stream DMA (2Ah) Table 119: Read Stream DMA Command (2Ah) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 177 Output Parameters To The Device Feature Current URG specifies an urgent transfer request. The Urgent bit specifies that the command should be completed in URG (bit7) the minimum possible time by the device and shall be completed within the specified Command Completion Time Limit.
Page 178 Feature Current The time allowed for the current command's completion is calculated as follows: Command Completion Time Limit = (content of the Feature register Pre- vious) * (Identify Device words (99:98)) useconds If the value is zero, the device shall use the Default Feature Previous CCTL (7:0) CCTL supplied with a previous Configure Stream command for this Stream ID.
Page 179 Feature Current SE (Stream Error) shall be set to one if an error has occurred during the execution of the command and the RC bit is set to one, In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error, and the Sector Count registers shall contain the number of consecutive sectors that may SE (Status, bit 5)
Page 180: Read Stream Pio (2Bh)
12.26 Read Stream PIO (2Bh) Table 120: Read Stream PIO (2Bh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 181 the device shall attempt to transfer the amount of data requested within the Command Completion Time Limit event if some data transferred is in error. Output Parameters To The Device Feature Current URG specifies an urgent transfer request. The Urgent bit specifies that the command should be completed in the minimum URG (bit7) possible time by the device and shall be completed within the...
Page 182 Feature Current The number of continuous sectors to be transferred low order, Sector Count Current bits (7:0) The number of continuous sectors to be transferred high Sector Count Previous order, bits (15:8). If zero is specified in the Sector Count register, then 65,536 sectors will be transferred.
Page 183: Read Verify Sectors (40H/41H)
12.27 Read Verify Sectors (40h/41h) Table 121: Read Verify Sectors (40h/41h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 184 Cylinder High/Low This is the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This is the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.
Page 185: Read Verify Sectors Ext (42H)
12.28 Read Verify Sectors Ext (42h) Table 122: Read Verify Sectors Ext command (42h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
Page 186 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 187: Recalibrate (1Xh)
12.29 Recalibrate (1xh) Table 123: Recalibrate (1xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 188: Security Disable Password (F6H)
12.30 Security Disable Password (F6h) Table 124: Security Disable Password (F6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 189: Security Erase Prepare
12.31 Security Erase Prepare Table 126: Security Disable Password (F3h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 190: Security Erase Unit (F4H)
12.32 Security Erase Unit (F4h) Table 127: Security Erase Unit (F4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 191 At this time the defective sector information and the reassigned sector information for the device are not updated. The security erase prepare command should be completed immediately prior to the Security Erase Unit command. If the device receives a Security Erase Unit command without a prior Security Erase Prepare command the device aborts the security erase unit command.
Page 192: Security Freeze Lock (F5H)
12.33 Security Freeze Lock (F5h) Table 129: Security Freeze Lock command (F5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 193: Security Set Password (F1H)
12.34 Security Set Password (F1h) Table 130: Security Set Password command (F1h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 194 Security Level Zero indicates High level. One indicates Maximum level. If the host sets High level and the password is forgotten, the Master Password can be used to unlock the device. If the host sets Maximum level and the user password is for- gotten, only a Security Erase Prepare/Security Unit command can unlock the device and all data will be lost.
Page 195: Security Unlock (F2H)
12.35 Security Unlock (F2h) Table 132: Security Unlock command (F2h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 196 The user can detect if the attempt to unlock the device has failed due to a mismatched password since this is the only reason that an abort error will be returned by the drive AFTER the password information has been sent to the device.
Page 197: Seek (7Xh)
12.36 Seek (7xh) Table 133: Seek command (7xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 198: Set Features (Efh)
12.37 Set Features (EFh) Table 134: Set Features command (EFh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 199: Set Transfer Mode
Note: After the power on reset or hard reset the device is set to the following features as default. Write cache Enable ECC bytes 4 bytes Read look-ahead Enable Reverting to power on defaults Disable Release interrupt Disable 12.37.1 Set Transfer mode When the Feature register is 03h (= Set Transfer mode) the Sector Count Register specifies the transfer mechanism.
Page 200 When Low RPM standby mode is the deepest Power Saving mode and the value in Sector Count register is between 40h and 7Fh, 120 ☯y ☯435 [sec] (default: 120 [sec]) = (x − 40h) 60 +600 (600 ☯y ☯4380) [sec] When Low RPM standby mode is the deepest Power Saving Mode and the value in Sector Count register is between 01h and 3Fh, where...
Page 201: Automatic Acoustic Management
12.37.4 Automatic Acoustic Management When Feature register is 42h (= Enable Automatic Acoustic Management), the Sector Count Register specifies the Automatic Acoustic Management level. Aborted C0-FEh Set to Normal Seek mode 80-BFh Set to Quiet Seek mode 00- 7Fh Aborted The device preserves enabling or disabling of Automatic Acoustic Management and the current Automatic Acous- tic Management level setting across all forms of reset, that is, Power on, Hardware, and Software Resets.
Page 202: Set Max Address (F9H)
12.38 Set Max ADDRESS (F9h) Table 135: Set Max ADDRESS command (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 203 changed to the native maximum address, the value placed in words (61:60) shall be 268,435,455 and the value placed in words (103:100) shall be the native maximum address. If a host protected area has been established by a Set Max Address Ext command, the device shall return command aborted.
Page 204: Set Max Set Password (Feature=01H)
12.38.1 Set Max Set Password (Feature=01h) Table 136: Set Max Set Password command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...
Page 205: Set Max Lock (Feature=02H)
12.38.2 Set Max Lock (Feature=02h) Table 138: Set Max Lock command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 206: Set Max Unlock (Feature = 03H)
12.38.3 Set Max Unlock (Feature = 03h) Table 139: Set Max Unlock command (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data...
Page 207: Set Max Freeze Lock (Feature = 04H)
12.38.4 Set Max Freeze Lock (Feature = 04h) Table 140: Set Max Freeze Lock (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data...
Page 208: Set Max Address Ext (37H)
12.39 Set Max Address Ext (37h) Table 141: Set Max Address Ext command (37h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
Page 209 Output parameters to the device Option bit for selection whether nonvolatile or volatile. B=0 is volatile condition. When B=1, MAX Address which is set by the Set Max Address Ext command is preserved by POR. When B=0, MAX Address which is set by the Set Max Address Ext command will be lost by POR.
Page 210: Set Multiple (C6H)
12.40 Set Multiple (C6h) Table 142: Set Multiple command (C6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 211: Sleep (E6H/99H)
12.41 Sleep (E6h/99h) Table 143: Sleep command (E6h/99h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 212: Function Set (B0H)
12.42 S.M.A.R.T. Function Set (B0h) Table 144: S.M.A.R.T. Function Set command (B0h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 213: Function Subcommands
12.42.1 S.M.A.R.T. Function Subcommands Code Subcommand S.M.A.R.T. Read Attribute Values S.M.A.R.T. Read Attribute Thresholds S.M.A.R.T. Enable/disable Attribute Autosave S.M.A.R.T. Save Attribute Values S.M.A.R.T. Execute Off-line Immediate S.M.A.R.T. Read Log Sector S.M.A.R.T. Write Log Sector S.M.A.R.T. Enable Operations S.M.A.R.T. Disable Operations S.M.A.R.T.
Page 214 12.42.1.4 S.M.A.R.T. Save Attribute Values (subcommand D3h) This subcommand causes the device to immediately save any updated Attribute Values to the device's Attribute Data sector regardless of the state of the Attribute Autosave feature. Upon receipt of the S.M.A.R.T. Save Attribute Values subcommand from the host, the device asserts BSY, writes any updated Attribute Values to the Attribute Data sector, clears BSY, and asserts INTRQ.
Page 215 Extended Comprehensive SMART Error See note S.M.A.R.T. Self-test Log Read Only Extended Self-test Log See note 80h-9Fh Host vendor specific Read/Write Note: Log addresses 03h and 07h are used by the Read Log Ext and Write Log Ext commands. If these log addresses are used with the SMART Read Log Sector command, the device shall return command aborted.
Page 216 If the device does not detect a Threshold Exceeded Condition, the device loads 4Fh into the Cylinder Low register and C2h into the Cylinder High register. If the device detects a Threshold Exceeded Condition, the device loads F4h into the Cylinder Low register and 2Ch into the Cylinder High register.
Page 217: Device Attribute Data Structure
12.42.2 Device Attribute Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values subcommand. All multibyte fields shown in these data structures are in byte ordering, that is, the least significant byte occupies the lowest numbered byte address location in the field.
Page 218 Attribute ID Numbers: Any nonzero value in the Attribute ID Number indicates an active attribute. The device supports following Attribute ID Numbers. Attribute Name Indicates that this entry in the data structure is not used Raw Read Error Rate Throughput Performance Spin Up Time Start/Stop Count Reallocated Sector Count...
Page 219: Total Time In Seconds To Complete Off-Line Data Collection Activity
Bit 7 Automatic Off-line Data Collection Status Automatic Off-line Data Collection is disabled. Automatic Off-line Data Collection is enabled. Bits 0–6 represent a hexadecimal status value reported by the device. Value Definition Off-line data collection never started. All segments completed without errors. Off-line data collection is suspended by the interrupting command.
Page 220: Device Attribute Thresholds Data Structure
Off-line Read Scanning implemented bit The device does not support Off-line Read Scanning The device supports Off-line Read Scanning Self-test implemented bit Self-test routing is not implemented Self-test routine is implemented Reserved (0) Selective self-test routine is not implemented 0 Selective self-test routine is not implemented 1 Selective self-test routine is implemented 12.42.2.7 S.M.A.R.T.
Page 221: Table 146.Device Attribute Thresholds Data Structure
The sequence of active Attribute Thresholds will appear in the same order as their corresponding Attribute Values. Table 147: Device Attribute Thresholds Data Structure Description Byte Offset Value Data Structure Revision Number 0010h 1st Device Attribute 30th Device Attribute 15Eh Reserved 16Ah Vendor specific...
Page 222: Log Directory
12.42.4 S.M.A.R.T. Log Directory The following table defines the 512 bytes that make up the S.M.A.R.T. Log Directory. The S.M.A.R.T. Log Direc- tory is S.M.A.R.T. Log Address zero and is defined as one sector long. Table 149: S.M.A.R.T. Log Directory Description Byte Offset...
Page 223: Table 150.Error Log Data Structure
12.42.5.4 Error log data structure The data format of each error log data structure is shown below. Table 151: Error log data structure Description Byte Offset 1st command data structure 2nd command data structure 3rd command data structure 4th command data structure 5th command data structure Error data structure 12.42.5.5 Command data structure...
Page 224: Self-Test Log Data Structure
Life time stamp (hours) The state field contains a value indicating the device state when command was issued to the device. Value State Unknown Sleep Standby Active/Idle S.M.A.R.T. Off-line or Self-test x5h-xAh Reserved xBh-xFh Vendor specific The value of ’x’ is vendor specific 12.42.6 Self-test log data structure The following table defines the 512 bytes that make up the Self-test log sector.
Page 225: Error Reporting
12.42.7 Error reporting The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device. Table 155: S.M.A.R.T. Error Codes Error condition Status Register Error Register A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being loaded into the Cylinder High and Cylinder Low registers.
Page 226: Standby (E2H/96H)
12.43 Standby (E2h/96h) Table 156: Standby (E2h/96h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 227 When the automatic power down sequence is enabled, the device will enter the Standby mode automatically if the time-out interval expires with no device access from the host. The time-out interval will be reinitialized if there is a drive access before the time-out interval expires. Deskstar 7K80 Hard Disk Drive Specification...
Page 228: Standby Immediate (E0H/94H)
12.44 Standby Immediate (E0h/94h) Table 157: Standby Immediate (E0h/94h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 229: Write Buffer (E8H)
12.45 Write Buffer (E8h) Table 158: Write Buffer (E8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 230: Write Dma (Cah/Cbh)
12.46 Write DMA (CAh/CBh) Table 159: Write DMA (CAh/CBh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 231 Sector Number This indicates the sector number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 0–7. (L = 1) Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High).
Page 232: Write Dma Ext (35H)
12.47 Write DMA Ext (35h) Table 160: Write DMA Ext Command (35h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 233 Cylinder High Current LBA (23:16) Cylinder High Previous LBA (47:40) Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error.
Page 234: Write Log Ext (3Fh)
12.48 Write Log Ext (3Fh) Table 161: Write Log Ext Command (3Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 235: Write Long (32H/33H)
12.49 Write Long (32h/33h) Table 162: Write Long (32h/33h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 236 Cylinder High/Low This indicates the cylinder number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This indicates the head number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 24–27.
Page 237: Write Multiple (C5H)
12.50 Write Multiple (C5h) Table 163: Write Multiple (C5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 238 Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains current the LBA bits 24–27.
Page 239: Write Multiple Ext (39H)
12.51 Write Multiple Ext (39h) Table 164: WriteMultiple Ext Command (39h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 240 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 241: Write Sectors (30H/31H)
12.52 Write Sectors (30h/31h) Table 165: Write Sectors command (30h/31h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 242 Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.
Page 243: Write Sectors Ext
12.53 Write Sectors Ext Table 166: Write Sectors Ext Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 244 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 245: Write Stream Dma (3Ah)
12.54 Write Stream DMA (3Ah) Table 167: Write Stream DMA Command (3Ah) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 246 Output Parameters To The Device Feature Current URG (bit7) URG specifies an urgent transfer request. The Urgent bit specifies that the command should be completed in the minimum possible time by the device and shall be completed within the specified Command Completion Time Limit. WC (bit6) WC specifies Write Continuous mode enabled.
Page 247: Write Stream Pio (3Bh)
12.55 Write Stream PIO (3Bh) Table 168: Write Stream PIO Command (3Bh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 248 Output Parameters To The Device Feature Current URG (bit7) URG specifies an urgent transfer request. The Urgent bit specifies that the command should be completed in the minimum possible time by the device and shall be completed within the specified Command Completion Time Limit. WC (bit6) WC specifies Write Continuous mode enabled.
Page 249 Input Parameters From The Device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 250 Deskstar 7K80 Hard Disk Drive Specification...
Page 251: Timings
13.0 Timings The timing of BSY and DRQ in Status Register are shown in the table below. Table 169: Time-out values INTERVAL START STOP TIME-OUT Power On Device Busy After Power On Status Register BSY=1 400 ns Power On Device Ready After Power On Status Register BSY=1 31 sec...
Page 252 Index 48-bit Address Feature ....................106 48-bit Address Feature Set ....................106 Abbreviations ........................11 Acoustics .........................68 Actuator ..........................19 Address Offset ........................104 Address Offset Feature ....................104 Addressing of registers ....................50 Advanced Power Managemen ..................102 Alternate Status Register ....................74 AT signal connector ......................33 Attribute thresholds ......................87 Attribute values .......................87 Attributes ........................87 Auto Reassign function ....................100...
Page 253 Corrosion test ........................59 CSA approval ........................69 C-TICK mark ........................70 Cylinder allocation ......................22, 23 Cylinder High Register ....................74 Cylinder Low Register ....................74 Data In commands ......................109 Data integrity ........................31 Data Out Commands .......................110 Data Register ........................75 Data Reliability .......................61 Data sheet ........................21, 22 Data transfer speed ......................27 DC power connector .......................33 DC power requirements ....................59...
Page 254 Features Register ......................77 Fixed-disk subsystem ......................19 Flammability ........................69 Flush Cache ........................130 Flush to Disk bit ......................107 Formatted capacity ......................21 Functional specification ....................17 General ..........................11 General features ......................15 General operation ......................81 Handle Streaming Error bit .....................108 Head disk assembly ......................19 Head disk assembly data ....................19 Heads unload ........................64 Host Terminating Write DMA ..................49 Humidity .........................58...
Page 255 Jumper settings .......................53 Labels, Identification ......................68 Latency, average ......................26 LBA addressing mode ....................84 Load/unload ........................61 Logical CHS addressing mode ..................84 Master Password setting ....................90 Mechanical positioning ....................24 Mechanical specifications ....................62 Mode transition time .......................29 Mounting hole locations ....................62, 63 Mounting orientation ......................64 Multi word DMA timings ....................41 Non-data commands .......................112 Not Sequential bit ......................108...
Page 256 Power consumption effiency ..................60 Power management commands ..................85 Power management features ...................85 Power supply current ......................60 Preventive maintenance ....................61 Protected Area .........................96 Read Continuous bit ......................108 Reassign function ......................100 References ........................11 Register initialization ......................82 Register set ........................73 Registers ..........................73 Reset response .........................81 Reset timings ........................38 S.M.A.R.T.
Page 257 Temperature ........................58 Threshold exceeded condition ..................87 Time-out values ......................247 Timings ...........................247 reset 38 UL approval ........................69 Ultra DMA timings ......................42 Urgent bit ........................107 Vibration .........................65 Weight ..........................62 World Wide Name Assignment ..................22 Write Buffer ........................225 Write cache function .......................99 Write Continuous bit .......................108 Deskstar 7K80 Hard Disk Drive Specification...
Page 258 References in this publication to Hitachi Global Storage Technologies products, programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates. Product information is provided for information pur- poses only and does not constitute a warranty.

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Hitachi 7K80 - Deskstar - Hard Drive Specifications

1 General

2 General Features of the Drive

3 Fixed-Disk Subsystem Description

4 Drive Characteristics

5 Defect Flagging Strategy

6 Electrical Interface Specification

7 Specification

8 General

9 Registers

10 General Operation

11 Command Protocol

12 Command Descriptions

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