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Sata Ii Optional Features; Asynchronous Signal Recovery; Device Power Connector Pin 11 Definition; Phy Event Counters - Hitachi HDS721050CLA362 Specifications

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SET ADDRESS MAX (EXT): The maximum LBA specified in SET ADDRESS MAX or SET ADDRESS
MAX EXT.
SET FEATURES (Write Cache Enable/Disable): The write cache enable/disable setting established by the
SET FEATURES command with subcommand code of 02h or 82h.
SET FEATURES (Set Transfer Mode): PIO, Multiword, and UDMA transfer mode settings established by
the SET FEATURES command with subcommand code of 03h.
SET FEATURES (Advanced Power Management Enable/Disable): The advanced power management
enable/disable setting established by the SET FEATURES command with subcommand code of 05h or 85h.
The advanced power management level established in the Sector Count register when advanced power
management is enabled (SET FEATURES subcommand code 05h) shall also be preserved.
SET FEATURES (Read Look-Ahead): The read look-ahead enable/disable setting established by the SET
FEATURES command with subcommand code of 55h or AAh.
SET FEATURES (Reverting to Defaults): The reverting to power-on defaults enable/disable setting
established by the SET FEATURES command with a subcommand code of CCh or 66h.
SET MULTIPLE MODE: The block size established with the SET MULTIPLE MODE command.

9.20 SATA II Optional Features

There are several optional features defined in SATA II. The following shows whether these features are
supported or not.
9.20.1

Asynchronous Signal Recovery

The device supports asynchronous signal recovery defined in SATA II.
9.20.2

Device Power Connector Pin 11 Definition

SATA II specification defines that Pin 11 of the power segment of the device connector may be used to
provide the host with an activity indication and disabling of staggered spin-up. The device does not support
both usage of Pin 11.
9.20.3

Phy Event Counters

Phy Event Counters are an optional feature to obtain more information about Phy level events that occur on the
interface. This information may aid designers and integrators in testing and evaluating the quality of the interface.
A device indicates whether it supports the Phy event counters feature in IDENTIFY (PACKET) DEVICE Word 76,
bit 10. The host determines the current values of Phy event counters by issuing the READ LOG EXT command
with a log page of 11h. The counter values shall not be retained across power cycles. The counter values shall
be preserved across COMRESET and software resets.
The counters defined can be grouped into three basic categories: those that count events that occur during Data
FIS transfers, those that count events that occur during non-Data FIS transfers, and events that are unrelated to
FIS transfers. Counters related to events that occur during FIS transfers may count events related to
host-to-device FIS transfers, device-to-host FIS transfers, or bi-directional FIS transfers. A counter that records
bi-directional events is not required to be the sum of the counters that record the same events that occur on
device-to-host FIS transfers and host-to-device FIS transfers.
Implementations that support Phy event counters shall implement all mandatory counters, and may support any
of the optional counters as shown in 0. Note that some counters may increment differently based on the speed
at which non-Data FIS retries are performed by the host and device. Implementations may record CRC and
non-CRC error events differently. For example, there is a strong likelihood that a disparity error may cause a
CRC error. Thus, the disparity error may cause both the event counter that records non-CRC events and the
event counter that records CRC events to be incremented for the same event. Another example implementation
difference is how a missing EOF event is recorded; a missing EOF primitive may imply a bad CRC even though
HITACHI Deskstar & CinemaStar 7K1000.B & Deskstar E7K1000 Hard Disk Drive specification
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