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8.2.8
General Registers (GRA, GRB)
The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each
channel.
Channel
Abbreviation
0
GRA0, GRB0
1
GRA1, GRB1
2
GRA2, GRB2
Bit
15
Initial value
1
R/W
Read/Write
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in TIOR.
When a general register is used as an output compare register, its value is constantly compared
with the 16TCNT value. When the two values match (compare match), the IMFA or IMFB flag is
set to 1 in TISRA/TISRB. Compare match output can be selected in TIOR.
When a general register is used as an input capture register, an external input capture signal are
detected and the current 16TCNT value is stored in the general register. The corresponding IMFA
or IMFB flag in TISRA/TISRB is set to 1 at the same time. The edges of the input capture signal
are selected in TIOR.
TIOR settings are ignored in PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are set as output compare registers (with no pin output) and initialized to H'FFFF
by a reset and in standby mode.
14
13
12
11
1
1
1
1
R/W
R/W
R/W
R/W
Function
Output compare/input capture register
10
9
8
7
1
1
1
1
R/W
R/W
R/W
R/W
6
5
4
3
1
1
1
1
R/W
R/W
R/W
R/W
2
1
0
1
1
1
R/W
R/W
R/W
237
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