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P8DDR is initialized to H'F0 in modes 1 to 4, and to H'E0 in modes 5 to 7, by a reset and in
hardware standby mode. In software standby mode P8DDR retains its previous setting. Therefore,
if a transition is made to software standby mode while port 8 is functioning as an input/output port
and a P8DDR bit is set to 1, the corresponding pin maintains its output state.
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data
for port 8. When port 8 functions as an output port, the value of this register is output. When a bit
in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned. When a
bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin logic level is read.
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
Bit
Initial value
Read/Write
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
188
7
6
—
—
1
1
—
—
Reserved bits
5
4
—
P8
P8
4
1
0
—
R/W
R/W
3
2
P8
P8
3
2
0
0
R/W
R/W
Port 8 data 4 to 0
These bits store data
for port 8 pins
1
0
P8
1
0
0
0
R/W
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