Table of Contents
Advertisement
φ
t
OSC1
V
CC
FWE
MD
to MD
2
0
RES
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried
out by means of RES input. The state of ports with multiplexed address functions and bus control output pins
(CSn, AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low),
and therefore these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, the mode programming setup time t
satisfied with respect to RES clearance timing.
See 22.4.6 Flash Memory Characteristics.
3.
(Example: Boot Mode → User Mode ↔ User Program Mode)
t
MDS
t
MDS
SWE set
Boot
Mode
*1
mode
change
Figure 19.18 Mode Transition Timing
Min 0µs
* 2
t
MDS
t
RESW
SWE
cleared
Mode
User
User program mode
*1
change
mode
3
User
User program
mode
mode
must be
MDS
617
Advertisement
Table of Contents
