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Write pulse application subroutine
Sub-Routine Write Pulse
WDT enable
Set PSU bit in FLMCR1
) µs
Wait (t
spsu
Set P bit in FLMCR1
) µs
Wait (t
sp
Clear P bit in FLMCR1
) µs
Wait (t
cp
Clear PSU bit in FLMCR1
) µs
Wait (t
cpsu
Disable WDT
End Sub
Note 6: Write Pulse Width
Write Time (tsp) µsec
Number of Writes (n)
1
30
2
30
3
30
4
30
5
30
6
30
7
200
8
200
9
200
10
200
11
200
12
200
13
200
998
200
999
200
1000
200
Note: Use a 10 µs write pulse for additional programming.
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming data must be provided in
RAM. The contents of the reprogram data area and additional-programming data area are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of
additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7. The wait times and value of N are shown in section 22.3.6, Flash Memory.
Reprogram Data Computation Table
Original Data
Verify Data
(D)
(V)
0
0
0
1
1
0
1
1
Figure 18.10 Program/Program-Verify Flowchart (128-Byte Programming)
Start of programming
Set SWE bit in FLMCR1
Wait (t
Store 128-byte program data in program
data area and reprogram data area
*
7
Start of programming
*
5
*
7
Consecutively write 128-byte data in reprogram
data area in RAM to flash memory
Programming halted
*
7
Set PV bit in FLMCR1
*
7
H'FF dummy write to verify address
Read verify data
Increment address
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
Reprogram data computation
Transfer reprogram data to reprogram data area
data verification completed?
NG
Clear PV bit in FLMCR1
Consecutively write 128-byte data in additional-
programming data area in RAM to flash memory
Write Pulse (Additional programming)
Clear SWE bit in FLMCR1
Wait (t
End of programming
Reprogram Data
Comments
(X)
1
Programming completed
0
Programming incomplete;
reprogram
1
1
Still in erased state; no action
Perform programming in the erased state.
START
Do not perform additional programming
on previously programmed addresses.
) µs
*
7
sswe
*
4
n= 1
m= 0
*
1
Sub-Routine-Call
See Note 6 for pulse width
Write pulse
) µs
Wait (t
*
spv
7
) µs
Wait (t
*
7
spvr
*
2
Write data =
NG
verify data?
m = 1
OK
NG
≥
6
n ?
OK
*
4
*
3
*
4
128-byte
OK
) µs
Wait (t
*
7
cpv
NG
≥
6
n?
OK
*
1
Sub-Routine-Call
NG
m= 0 ?
OK
Clear SWE bit in FLMCR1
) µs
cswe
Additional-Programming Data Computation Table
Reprogram Data
Verify Data
(X')
(V)
Programming Data (Y)
0
0
0
1
1
0
1
1
n ← n + 1
Reprogram
*
7
NG
n ≥ N?
OK
) µs
Wait (t
*
7
cswe
Programming failure
Additional-
Comments
Additional programming
0
to be executed
1
Additional programming
not to be executed
1
Additional programming
not to be executed
Additional programming
1
not to be executed
551
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